NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 701

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

18—Intel
18.12 Data Return Behavior of Hub Interface
18.13 Performance Targets
18.13.1 Introduction
18.13.2 Definitions and Assumptions
November 2007
Order Number: 300641-004US
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6300ESB ICH
Initiated Reads
For all Hub Interface initiated memory read cycles targeting PCI/PCI-X, the Intel
6300ESB ICH ensures a return length of a naturally aligned 128-bytes. When a request
is less than 128 bytes and within a single 128-byte line, the Intel
generates one completion. When the request crosses a line, the Intel
returns multiple completions, broken on 128-byte line boundaries, until the request is
fulfilled.
The Intel
command that is longer than a dWord and is qWord aligned.
The Intel
number of qWords. The Intel
requests be returned as qWords and never dwords. For read streaming to work, the
Intel
on a cache line boundary (64 or 128 bytes).
This information is organized into three sections. The first section specifies general bus
timings. The second specifies single active master throughputs. The third specifies
concurrent performance when multiple agents are generating requests from both
busses.
Bandwidth tests are sustained throughput tests. The system may be run until it reaches
steady state and then run longer with the bandwidth measured.
The system under test uses 4x, 8 bit, HL 1.5.
Memory bandwidth in the system under test is sufficient to service the requirements of
the PCI-X so that contention for memory and other system resources is not a
performance bottleneck.
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All units that have a configuration space that could be accessed by SM Bus have a
“1 command only” depth. This helps ensure that multiple requests are not
outstanding, minimizing any possibility of SM Bus accesses being stuck.
The Intel
hub ID/pipe ID on the internal bus, ensuring that no space has to be reserved to
re-order the completion data. Only cycles that have a unique hub ID/pipe ID may
be launched simultaneously, and their completions may return in any order.
Any request from SM Bus (or the Hub Interface) that targets the I/OxAPIC must be
able to complete, even when the I/OxAPIC has an interrupt to deliver to the Hub
Interface. Otherwise, the completion for the SM Bus/Hub Interface access is
blocked behind the I/OxAPIC request to the Hub Interface, and it does not finish.
System management software must ensure that the SM Bus does not generate
accesses PCI. When this occurs and PCI is blocked, the SM Bus is blocked.
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6300ESB ICH requires that the driving agent only disconnect read completions
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6300ESB ICH only generates qWord aligned reads whose length is a multiple
6300ESB ICH does not return a dWord completion on a memory read
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6300ESB ICH does not launch successive requests that have the same
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6300ESB ICH requires that the completions for these
Intel
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6300ESB I/O Controller Hub
6300ESB ICH
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6300ESB ICH
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