NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 305

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

7—Intel
7.1.26
Table 172. Offset 44 - 45h: DEVICE_HIDE—Secondary PCI Device Hiding Register
November 2007
Order Number: 300641-004US
15:9
Bits
Default Value:
7:6
8
5
4
3
2
1
0
®
Device:
Offset:
6300ESB ICH
HIDE_DEV3
HIDE_DEV2
HIDE_DEV1
HIDE_DEV0
Offset 44 - 45h: DEVICE_HIDE—Secondary PCI
Device
Hiding Register (HUB-PCI—D30:F0)
This register allows software to “hide” PCI devices. Specifically, when PCI devices are
hidden, the configuration space is not accessible because the PCI IDSEL pin does not
assert. The Intel
through 3).
Hiding a PCI device may be useful for debugging, bug work-arounds, and system
management support. Devices should only be hidden during initialization before any
configuration cycles are run. This ensures that the device is not in a semi-enable state.
(HUB-PCI—D30:F0)
Reserved
Reserved
Reserved
Reserved
Reserved
30
44-45h
00h
Name
®
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Same as bit 0 of this register, except for device 3 (AD{19]).
Same as bit 0 of this register, except for device 2 (AD{18]).
Same as bit 0 of this register, except for device 1 (AD[17])
When this bit is set, it hides device 0 on the PCI bus. This is
done by masking the IDSEL (keeping it low) for configuration
cycles to that device. Since the device will not see its IDSEL
go active, it will not respond to PCI configuration cycles and
the processor will think the device is not present. AD[16] is
used as IDSEL for device 0.
When this bit is a 0, the PCI configuration cycles for this slot
are not affected.
6300ESB ICH supports the ability to hide four external devices (0
Power Well:
Description
Attribute:
Function:
Size:
0
Read/Write
16-bit
00h
Intel
®
6300ESB I/O Controller Hub
Access
305
DS