NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 322

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

8.1.16
Table 196. Offset PIRQA - 60h: PIRQ[n]_ROUT—PIRQ[A,B,C,D] Routing Control
Intel
DS
322
Bits
Default Value:
6:4
3:0
7
®
6300ESB I/O Controller Hub
Device:
Offset:
IRQEN: Interrupt
Routing Enable
IRQ Routing
Offset PIRQA - 60h: PIRQ[n]_ROUT—
PIRQ[A,B,C,D]
Routing Control (LPC I/F—D31:F0)
(LPC I/F—D31:F0)
Reserved
31
PIRQA - 60h, PIRQB -
61h,
PIRQC - 62h, PIRQD -
63h
80h
Name
0 = The corresponding PIRQ is routed to one of the ISA-
1 = The PIRQ is not routed to the 8259.
NOTE: BIOS must program this bit to “0” during POST for any
Reserved.
(ISA compatible)
Bits Mapping
0000 = Reserved 1000 = Reserved
0001 = Reserved 1001 = IRQ9
0010 = Reserved 1010 = IRQ10
0011 = IRQ3
0100 = IRQ4
0101 = IRQ5
0110 = IRQ6
0111 = IRQ7
compatible interrupts specified in bits[3:0].
of the PIRQs that are being used. The value of this bit
may subsequently be changed by the OS when setting
up for I/O APIC interrupt delivery mode.
Bits Mapping
1011 = IRQ11
1100 = IRQ12
1101 = Reserved
1110 = IRQ14
1111 = IRQ15
Description
Attribute:
Function:
Size:
0
Read/Write
8-bit
Order Number: 300641-004US
Intel
®
6300ESB ICH—8
November 2007
Access
R/W
R/W