NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 481

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

10—Intel
10.2.4
Table 375. Offset Base + (06 - 07h): FRNUM—Frame Number Register
10.2.5
Table 376. Offset Base + (08 - 0Bh): FRBASEADD—Frame List Base Address
November 2007
Order Number: 300641-004US
15:1
10:0
31:1
11:0
Bits
Bits
Default Value:
Default Value:
1
2
Note: Bits [10:0] of this register contain the current frame number included in the frame SOF
Note: This register must be written as a word. Byte writes are not supported. This register
Note: This 32-bit register contains the beginning address of the Frame List in the system
Device:
Device:
®
Offset:
Offset:
Index/Frame Number
6300ESB ICH
Frame List Current
Base Address
Offset Base + (06 - 07h): FRNUM—Frame Number
Register
packet. This register reflects the count value of the internal frame number counter. Bits
[9:0] are used to select a particular entry in the Frame List during scheduled execution.
This register is updated at the end of each frame time.
cannot be written unless the Host Controller is in the STOPPED state as indicated by the
HCHalted bit (USBSTS register). A write to this register while the Run/Stop bit is set
(USBCMD register) is ignored.
Offset Base + (08 - 0Bh): FRBASEADD—Frame List
Base Address
memory. HCD loads this register prior to starting the schedule execution by the Host
Controller. When written, only the upper 20 bits are used. The lower 12 bits are written
as ’0’ (4-Kbyte alignment). The contents of this register are combined with the frame
number counter to enable the Host Controller to step through the Frame List in
sequence. The two least significant bits are always 00. This requires DWORD alignment
for all list entries. This configuration supports 1024 Frame List entries.
Reserved
Reserved
29
Base + (06-07h)
0000h
Name
29
Base + (08-0Bh)
Undefined
Name
Reserved.
Provides the frame number in the SOF Frame. The value in
this register increments at the end of each time frame
(approximately every 1 ms). In addition, bits [9:0] are used
for the Frame List current index and correspond to memory
address signals [11:2].
These bits correspond to memory address signals [31:12],
respectively.
Reserved.
Description
Description
Attribute:
Attribute:
Function:
Function:
Size:
Size:
X
Read/Write
16-bit
X
Read/Write
32-bit
Intel
®
6300ESB I/O Controller Hub
Access
Access
R/W
R/W
481
DS