NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 267

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

5—Intel
5.20.2.14Input Slot 0: Tag Phase
5.20.2.15Input Slot 1: Status Address Port/Slot Request Bits
Table 139. Input Slot 1 Bit Definitions
November 2007
Order Number: 300641-004US
®
6300ESB ICH
Input slot 0 consists of a codec ready bit (bit 15), and slot valid bits for each
subsequent slot in the frame (bits [14:3]).
The codec ready bit within slot 0 (bit 15) indicates whether the codec on the AC-link is
ready for register access (digital domain). When the codec ready bit in slot 0 is a zero,
the codec is not ready for register access. When the AC-link codec ready bit is a 1, it
indicates that the AC-link and codec control and status registers are in a fully
operational state. The codec ready bits are visible through the Global Status register of
the Intel
register in the codec to determine exactly which subsections, when any, are ready.
Bits [14:3] in slot 0 indicate which slots of the input stream to the Intel
contain valid data, just as in the output frame. The remaining bits in this slot are
stuffed with zeros.
The status port is used to monitor status of codec functions including, but not limited
to, mixer settings and power management.
Slot 1 must echo the control register index, for historical reference, for the data to be
returned in slot 2, assuming that slots 1 and 2 had been tagged valid by the codec in
slot 0.
For variable sample rate output, the codec examines its sample rate control registers,
the state of its FIFOs, and the incoming SDOUT tag bits at the beginning of each audio
output frame to determine which SLOTREQ bits to set active (low). SLOTREQ bits
asserted during the current audio input frame signal which output slots require data
from the controller in the next audio output frame. For fixed 48 KHz operation the
SLOTREQ bits are always set active (low) and a sample is transferred each frame.
For variable sample rate input, the tag bit for each input slot indicates whether valid
data is present or not.
NOTE: Slot 3 Request and Slot 4 Request bits must be the same value, i.e. set or cleared in
18:1
[8:2
1:0
Bit
19
11
10
2
9
}
Reserved (Set to zero)
Control Register Index (Stuffed with zeros when tagged as invalid)
Slot 3 Request: PCM Left Channel
Slot 4 Request: PCM Right Channel
Slot 5 Request: Modem Line 1
Slot 6-12 Request: Not Implemented
Reserved (Stuffed with zeros)
tandem. This is also true for the Slot 7 and Slot 8 Request bits, as well as the Slot 6 and
Slot 9 Request bits.
®
6300ESB ICH. Software must further probe the Powerdown Control/Status
(1)
(1)
Description
Intel
®
6300ESB I/O Controller Hub
®
6300ESB ICH
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