NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 741

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

20—Intel
20.1.4
November 2007
Order Number: 300641-004US
10:9
Bits
Default Value:
3:0
15
14
13
12
11
8
7
6
5
4
Table 664. Offset 06 - 07h: STS—Device Status Register (SATA–D31:F2)
Device:
®
DEVSEL# Timing Status
Master Data Parity Error
User Definable Features
Offset:
Signaled System Error
Received Master-Abort
Received Target-Abort
Signaled Target-Abort
Detected Parity Error
Capabilities List (CL)
6300ESB ICH
Fast Back-to-Back
Detected (DPD)
66MHz Capable
Status (RMA)
Status (RTA)
Status (STA)
Offset 06 - 07h: STS—Device Status Register
(SATA–D31:F2)
Reserved
Capable
(DEVT)
31
06-07h
02B0h
Name
(UDF)
(DPE)
(SSE)
0 = No Parity error detected by SATA controller.
1 = SATA Controller detects a parity error on its interface.
This bit is set by the Intel
SERR# (internally). The SERR_EN bit (bit 8 in the Command
Register) must be ’1’ for this bit to be set. The following
conditions can cause the generation of SERR#:
A parity error is seen on address, command, or data (if the
data was targeting the EHC) on the internal interface to the
USBe host controller due to a parity error on Hub Interface
and bit 6 of the Command register is set to 1.
An EHC-initiated memory read results in a completion packet
with a status other than successful on Hub Interface. The
SERR on Aborts Enable bit (bit 3, offset 84h) must also be set
in this case.
Software clears this bit by writing a ‘1’ to this bit location.
0 = 0 Cleared by writing a ’1’ to it.
1 = Bus Master IDE interface function, as a master, generated
Set when the SATA Controller receives a target abort to a
cycle it generated.
Reserved as ‘0’.
01 = Hardwired; Controls the device select time for the SATA
Controller’s PCI interface.
Set when the SATA Controller, as a master, either detects a
parity error or sees the parity error line asserted, and the
parity error response bit (bit 6 of the command register) is
set. For the Intel
read completions when there is a parity error.
Reserved as ‘1’.
Reserved as ‘0’.
Reserved as ‘1’.
Indicates the presence of a capabilities list. This bit is
hardwired to a ‘1’ indicating the presence of a valid
capabilities pointer at offset 34h.
Reserved
a master-abort.
®
6300ESB ICH, this bit may only be set on
Description
®
Attribute:
Function:
6300ESB ICH whenever it signals
Size:
2
Read/Write Clear, Read-Only
16-bit
Intel
®
6300ESB I/O Controller Hub
Access
R/WC
R/WC
R/WC
RO
RO
RO
RO
RO
RO
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