NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 663

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

18—Intel
18.6.1.13Offset 1E: SSTS—Secondary Status
November 2007
Order Number: 300641-004US
10:9
Bits
15
14
13
12
11
8
7
6
Table 596. Offset 1E: SSTS—Secondary Status (Sheet 1 of 2)
Note: For the writable bits in this register, writing a ’1’ clears the bit. Writing a ’0’ to the bit
Note: RASERR# will be asserted based on activity of bits 15:11, 8.
Abort (STA)
Abort (RTA)
Parity Error
Error (RSE)
®
Data Parity
Fast Back-
Device
DEVSEL#
Offset
Detected
Detected
Reserved
Received
Received
Received
Signaled
Capable
to-Back
System
6300ESB ICH
Master
Timing
Name
(RMA)
Target
Target
(DPD)
(DVT)
(DPE)
Abort
(FBC)
Error
has no effect.
28
1E
This bit is set to a ’1’ whenever the Intel
detects a address or data parity error on the PCI-X bus. This
bit gets set even when the Parity Error Response bit (bit ’0’ of
offset 3E-3F) is not set.
The Intel
is received on PCI-X.
This bit is set whenever the Intel
an initiator on the PCI-X bus and the cycle is master-aborted.
For Hub Interface packets that have completion required, this
should also cause a target abort completion status to be
returned and set the Signaled Target Abort bit in the primary
status register.
This bit is set whenever the Intel
an initiator on PCI-X and a cycle is target-aborted on PCI-X.
For “completion required” Hub Interface packets, this event
should force a completion status of “target abort” on the Hub
Interface and set the Signaled Target Abort in the Primary
Status Register.
This bit is set to ’1’ when the Intel
a target on the PCI-X Bus and signals a target abort.
Indicates that the Intel
decode time to all cycles targeting the Hub Interface.
The Intel
are true:
Indicates that the secondary interface of the Intel
ICH may receive fast back-to-back cycles.
Reserved.
• The Intel
• PERR# is detected asserted or a parity error is detected
• The Parity Error Response Enable bit in the Bridge Control
internally.
Register (bit 0, offset 3Eh) is set.
®
®
6300ESB ICH sets this bit when a SERR# assertion
6300ESB ICH sets this bit when all of the following
®
6300ESB ICH is the initiator on PCI-X.
®
Description
6300ESB ICH responds in medium
®
®
®
6300ESB ICH is acting as
6300ESB ICH is acting as
6300ESB ICH is acting as
Attribute:
Function
®
6300ESB ICH
Size:
®
0
Read/Write Clear
16-bit
6300ESB
Intel
®
Reset
Value
6300ESB I/O Controller Hub
01
0
0
0
0
0
0
1
0
Access
R/WC
R/WC
R/WC
R/WC
R/WC
R/WC
RO
RO
RO
663
DS