NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 144

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

Intel
DS
144
®
6300ESB I/O Controller Hub
Because the S1 state will have the STPCLK# signal active, the STPCLK# signal can be
connected to both processors. However, for ACPI implementations, the BIOS must
indicate that the 6300ESB only supports the C1 state for dual-processor designs.
In going to the S1 state, multiple Stop-Grant cycles will be generated by the CPUs. The
Intel 6300ESB also has the option to assert the CPU’s SLP# signal (CPUSLP#). It is
assumed that prior to setting the SLP_EN bit (which causes the transition to the S1
state), the CPUs will not be executing code that is likely to delay the Stop-Grant cycles.
In going to the S3, S4, or S5 states, the system will appear to pass through the S1
state; thus, STPCLK# and SLP# are also used. During the S3, S4, and S5 states, both
processors will lose power. Upon exit from those states, the processors will have their
power restored.
Order Number: 300641-004US
Intel
®
6300ESB ICH—5
November 2007