NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 273

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

5—Intel
5.20.6
Table 141. AC-link State during PXPCIRST#
5.20.7
November 2007
Order Number: 300641-004US
AC_RST#
AC_SDOUT
AC_SYNC
BIT_CLK
AC_SDIN[2:0]
NOTES:
1. Intel
2. The pull-down resistors on these signals are only enabled when the AC-Link Shut Off bit in the AC’97 Global
3. AC_RST# will be held low during S3-S5. It cannot be programmed high during a suspend state.
4. BIT_CLK and AC_SDIN[2:0] are driven low by the codecs during normal states. When the codec is powered
during system reset. These signals may have weak pullups/pulldowns on them. The Intel
outputs will be driven to the appropriate level prior to AC_RST# being deasserted, preventing a codec from
entering test mode. Straps are tied to the core well to prevent leakage during a suspend state.
Control Register is set to 1. All other times, the pull-down resistor is disabled.
during suspend states, it will hold these signals low. However, when the codec is not present, or not powered
in suspend, external pull-down resistors are required.
Signal
®
®
6300ESB ICH
6300ESB ICH core well outputs are used as strapping options for the Intel
System Reset
Table 141
conditions.
The transition of AC_RST# to the deasserted state will only occur under driver control.
In the S1 sleep state, the state of the AC_RST# signal is controlled by the AC’97 Cold
Reset# bit (bit 1) in the Global Control register. AC_RST# will be asserted (low) by the
Intel
Hardware will never deassert AC_RST# (i.e., never deasserts the Cold Reset# bit)
automatically. Only software may deassert the Cold Reset# bit, and hence the
AC_RST# signal. This bit, while it resides in the core well, will remain cleared upon
return from S3/S4/S5 sleep states. The AC_RST# pin will remain actively driven from
the resume well as indicated.
Hardware Assist to Determine AC_SDIN Used Per
Codec
Software first performs a read to one of the audio codecs. The read request goes out on
AC_SDOUT. Since under our micro-architecture only one read may be performed at a
time on the link, eventually the read data will come back on one of the AC_SDIN[2:0]
lines.
•
•
•
•
•
Resume
Core
Core
Core
Resume
Power
RSMRST# (system reset, including the reset of the resume well and PXPCIRST#)
Mechanical power up (causes PXPCIRST#)
Write to CF9h hard reset (causes PXPCIRST#)
Transition to S3/S4/S5 sleep states (causes PXPCIRST#)
Write to AC’97 Cold Reset# bit in the Global Control Register.
Plane
®
1
6300ESB ICH under the following conditions:
3
indicates the states of the link during various system reset and sleep
Outpu
Outpu
Outpu
Input
Input
I/O
t
t
t
PXPCIRST#/
Driven by
Driven by
During
codec
codec
Low
Low
Low
PXPCIRST#/
Running
Running
Running
Running
After
Low
(Hub Interface)
Cold Reset bit
Low
Low
Low
Low
S1
Intel
2,4
2,4
®
6300ESB ICH, sampled
®
6300ESB I/O Controller Hub
®
Low
Low
6300ESB ICH
Low
Low
Low
S3
2,4
2,4
S4/S5
Low
Low
Low
Low
Low
2,4
2,4
273
DS