NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 360

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

8.3.3
Table 236. Counter Access Ports Register
8.4
8.4.1
Table 237. PIC Registers
Intel
DS
360
Bits
Default Value:
7:0
I/O Address:
®
6300ESB I/O Controller Hub
Device:
Counter Port
Counter Access Ports Register
8259 Interrupt Controller (PIC) Registers
Interrupt Controller I/O MAP
The interrupt controller registers are located at 20h and 21h for the master controller
(IRQ0 - 7), and at A0h and A1h for the slave controller (IRQ8 - 13). These registers
have multiple functions, depending upon the data written to them. Listed in the table
below are descriptions of the different register possibilities for each address.
31
Counter 0 - 40h,
Counter 1 - 41h,
Counter 2 - 42h
All bits undefined
Name
Port
20h
21h
A0h
34h, 38h, 3Ch
2Dh, 31h,
A4h, A8h,
ACh, B0h,
B4h, B8h,
24h, 28h,
2Ch, 30h,
25h, 29h,
35h, 39h,
Aliases
3Dh
BCh
Each counter port address is used to program the 16-bit
Count Register. The order of programming, either LSB only,
MSB only, or LSB then MSB, is defined with the Interval
Counter Control Register at port 43h. The counter port is also
used to read the current count from the Count Register, and
return the status of the counter programming following a
Read Back Command.
Master PIC ICW1 Init. Cmd Word 1
Register
Master PIC OCW2 Op Ctrl Word 2
Register
Master PIC OCW3 Op Ctrl Word 3
Register
Master PIC ICW2 Init. Cmd Word 2
Register
Master PIC ICW3 Init. Cmd Word 3
Register
Master PIC ICW4 Init. Cmd Word 4
Register
Master PIC OCW1 Op Ctrl Word 1
Register
Slave PIC ICW1 Init. Cmd Word 1
Register
Slave PIC OCW2 Op Ctrl Word 2 Register
Slave PIC OCW3 Op Ctrl Word 3 Register
Register Name/Function
Description
Attribute:
Function:
Size:
0
Read/Write
8-bit
Order Number: 300641-004US
001XXXXXb
001XXXXXb
X01XXX10b
X01XXX10b
Undefined
Undefined
Undefined
Undefined
Default
Value
01h
00h
Intel
®
6300ESB ICH—8
November 2007
Access
R/W
Type
R/W
R/W
R/W
WO
WO
WO
WO
WO
WO
WO