NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 164

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

Table 74.
5.11.10.2Programmable Interrupt Controller (PIC) Reserved Bits
Intel
DS
164
NOTES:
I/O
Add
1. The OCW1 register must be read before entering ALT access mode.
2. Bits 5, 3, 1, and 0 return zero.
08h
20h
r
®
6300ESB I/O Controller Hub
Rd
12
of
#
6
s
Acces
Write Only Registers with Read Paths in ALT Access Mode (Sheet 2 of
2)
10
11
12
Many bits within the PIC are reserved, and must have certain values written in order for
the PIC to operate properly. Therefore, there is no need to return these values in ALT
access mode. When reading PIC registers from 20h and A0h, the reserved bits shall
return the values listed in the following table.
s
1
2
3
4
5
6
1
2
3
4
5
6
7
8
9
Restore Data
DMA Chan 0-3 Command
DMA Chan 0-3 Request
DMA Chan 0 Mode: Bits(1:0) =
“00”
DMA Chan 1 Mode: Bits(1:0) =
“01”
DMA Chan 2 Mode: Bits(1:0) =
“10”
DMA Chan 3 Mode: Bits(1:0) =
“11”.
PIC ICW2 of Master controller
PIC ICW3 of Master controller
PIC ICW4 of Master controller
PIC OCW1 of Master controller
PIC OCW2 of Master controller
PIC OCW3 of Master controller
PIC ICW2 of Slave controller
PIC ICW3 of Slave controller
PIC ICW4 of Slave controller
PIC OCW1 of Slave controller
PIC OCW2 of Slave controller
PIC OCW3 of Slave controller
Data
2
1
1
Add
I/O
CAh
CCh
D0h
CEh
r
Rd
of
#
2
2
2
6
s
Acces
s
1
2
1
2
1
2
1
2
3
4
5
6
Restore Data
DMA Chan 6 base count low byte
DMA Chan 6 base count high byte
DMA Chan 7 base address low
byte
DMA Chan 7 base address high
byte
DMA Chan 7 base count low byte
DMA Chan 7 base count high byte
DMA Chan 4-7 Command
DMA Chan 4-7 Request
DMA Chan 4 Mode: Bits(1:0) =
“00”
DMA Chan 5 Mode: Bits(1:0) =
“01”
DMA Chan 6 Mode: Bits(1:0) =
“10”
DMA Chan 7 Mode: Bits(1:0) =
“11”.
Order Number: 300641-004US
Intel
Data
®
6300ESB ICH—5
November 2007
2