NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 449

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

9—Intel
November 2007
Order Number: 300641-004US
Bits
Default Value:
9:8
10
7
6
5
Table 342. IDE_TIM—IDE Timing Register (IDE—D31:F1) (Sheet 2 of 3)
®
Device:
Drive 1 Prefetch/Posting
Offset:
6300ESB ICH
Drive 1 IORDY Sample
Recovery Time (RCT)
Drive 1 DMA Timing
Fast Non-Data PIO
Point Enable (IE1)
Enable (DTE1)
Enable (PPE1)
(FNDPIO)
31
Primary:
Secondary: 42-43h
0000h
Name
40-41h
Software sets this read/write bit to 1 to enable the fast PIO
accesses for non Data Register accesses. When this bit is a 1,
the timings for PIO cycles to IDE drive registers other than
offset 170h or 1F0h will run using PIO data timings. Default
for this bit is 0. This mode should only be enabled for UDMA-
based IDE protocols.
When this bit is set to '1', bit 14 in this register (Drive 1
Timing Register Enable) must be either: '0' to force
equivalent timings for both the master and slave devices, or
'1' with equivalent timings programmed in the Slave IDE
Timing register. Bits 7 and 3 in this register must be '0' in
order to utilize this mode. Likewise, bits 4 and 0 of this
register must be programmed to '1'; bits 5 and 1 must be
programmed to the same value. The timing parameters must,
of course, be compatible with each of the devices on the
channel. The two drives must be programmed for the same
timings because some non-data register accesses must be
received by both the master and slave devices
simultaneously, and because different settings would result in
timings that change in the middle of some of the non-data
accesses.
Bits 13:12 and bits 9:8 determine the cycle timings. Bits 6
and 2 do not apply to the non-data accesses.Note that the
non-data accesses are not posted, but that accesses to the
Data register may be posted. Therefore, the non-data
accesses may actually be limited by the access turn-around
achievable on Hub Interface rather than the RCT timing.
The setting of these bits determines the minimum number of
PCI clocks between the last IORDY sample point and the
IOR#/IOW# strobe of the next cycle.
00 = 4 clocks
01 = 3 clocks
10 = 2 clocks
11 = 1 clock
0 = Disable.
1 = Enable the fast timing mode for DMA transfers only for
0 = Disable.
1 = Enable Prefetch and posting to the IDE data port for this
0 = Disable IORDY sampling for this drive.
1 = Enable IORDY sampling for this drive.
this drive. PIO transfers to the IDE data port will run in
compatible timing.
drive.
Description
Attribute:
Function:
Size:
1
Read/Write
16-bit
Intel
®
6300ESB I/O Controller Hub
Access
R/W
R/W
R/W
R/W
449
DS