NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 298

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

7.1.19
Table 165. Offset 24h - 25h: PREF_MEM_BASE—Prefetchable Memory Base
Intel
DS
298
15:4
Bits
Default Value:
3:0
®
6300ESB I/O Controller Hub
Note: When the Hub Interface is acting as the initiator, it will not respond as a target.
Device:
Offset:
Prefetchable Memory
Address Base
Offset 24h - 25h: PREF_MEM_BASE—Prefetchable
Memory
Base Register (HUB-PCI—D30:F0)
Offset Address:
Default Value:
This register defines the Base Address of the Hub Interface-to-PCI prefetchable
memory range. Since the Intel
accesses to PCI, the Intel
when not to accept cycles as a target.
This register must be initialized by the config software. For the purpose of address
decode, address bits AD[19:0] are assumed to be FFFFFh. Thus, the top of the defined
memory address range will be aligned to a 1 Mbyte boundary.
Register (HUB-PCI—D30:F0)
Reserved
30
24h-25h
0000FFF0h
Name
Defines the base address of the prefetchable memory address
range for PCI. These 12 bits correspond to address bits
31:20.
Reserved.
24h-25h
0000FFF0h
®
6300ESB ICH will only use this information for determining
®
6300ESB ICH will forward all Hub Interface memory
Description
Attribute:
Function:
Size:
Attribute:
Size:
0
Read/Write
16-bit
R/W
16-bit
Order Number: 300641-004US
Intel
®
6300ESB ICH—7
November 2007
Access
R/W
RO