NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 825
NHE6300ESB S L7XJ
Manufacturer Part Number
NHE6300ESB S L7XJ
Description
Manufacturer
Intel
Datasheet
1.NHE6300ESB_S_L7XJ.pdf
(848 pages)
Specifications of NHE6300ESB S L7XJ
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23—Intel
Testability
23.1
Table 731. Test Mode Selection
.
November 2007
Order Number: 300641-004US
Note: RTCRST# can be driven low any time after PXPCIRST# is inactive.
®
6300ESB ICH
Test Mode Description
The Intel
XOR Chain test mode. Driving RTCRST# low for a specific number of PCI clocks while
PWROK is high will activate a particular test mode as described in
Figure 66
rising edge of the RTCRST# after being asserted for a specific number of PCI clocks
while PWROK is active. To change test modes, the same sequence should be followed
again. To restore the Intel
with RTCRST# being asserted so that no test mode is selected as specified in
Table
RTCRST# driven low after
Number of PCI Clocks
731.
PWROK active
®
illustrates entry into a test mode. A particular test mode is entered upon the
6300ESB ICH supports two types of test modes, a tri-state test mode and a
15 - 42
43 - 51
9 - 13
>60
<4
14
52
53
59
60
4
5
6
7
8
®
6300ESB ICH to normal operation, execute the sequence
Number of PCI Clocks after
RTCRST# driven high
N/A
N/A
N/A
N/A
N/A
3
3
3
3
3
3
3
3
3
3
Intel
Reserved. DO NOT ATTEMPT
Reserved. DO NOT ATTEMPT
No Test Mode Selected
No Test Mode Selected
No Test Mode Selected
®
XOR Chain 4 Bandgap
6300ESB I/O Controller Hub
Table
XOR Chain 1
XOR Chain 2
XOR Chain 3
XOR Chain 4
XOR Chain 6
XOR Chain 5
XOR Chain 7
Test Mode
Long XOR
All “Z”
731.
23
825
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