NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 226

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

5.18.4.2 Asynchronous List Execution
5.18.4.2.1 Read Policies for Asynchronous DMA
Table 111. Read Policies for Asynchronous DMA
Intel
DS
226
®
6300ESB I/O Controller Hub
Note: The ADE does not fetch data when a QH is encountered in the Ping state. An Ack
Note: Once the ADE checks the length of an asynchronous packet against the remaining time
Note: Once the ADE detects an “empty” asynchronous schedule as described in Section 4 of
The Asynchronous DMA engine contains buffering for two control structures (two
transactions). By implementing two entries, the EHC is able to pipeline the memory
accesses for the next transaction while executing the current transaction on the USB
ports.
The Asynchronous DMA engine performs reads for the following structures.
The EHC Asynchronous DMA Engine (ADE) does not generate accesses to main memory
unless all four of the following conditions are met. (Note that the ADE may be active
when the periodic schedule is actively executed, unlike the description in the EHCI
specification; since the EHC contains independent DMA engines, the ADE may perform
memory accesses interleaved with the PDE accesses.)
handshake in response to the Ping results in the ADE writing the QH to the Out state,
which results in the fetching and delivery of the Out Data on the next iteration through
the asynchronous list.
in the microframe (late-start check) and decides that there is not enough time to run it
on the wire, then the EHC stops all activity on the USB ports for the remainder of that
microframe.
the EHCI specification, it implements a waking mechanism like the one in the example.
The amount of time that the ADE “sleeps” is 10 µs ± 30 ns.
qTD
Queue Head
Out Data
•
•
•
•
Structure
The HCHalted bit is 0 (memory space, offset 04h, bit 12). Software clears this bit
indirectly by setting the RUN/STOP bit to 1.
The Asynchronous Schedule Status bit is 1 (memory space, offset 04h, bit 15).
Software sets this bit indirectly by setting the Asynchronous Schedule Enable Bit to
1. See
EHCI Status”
The Bus Master Enable bit is 1 (configuration space, offset 04h, bit 2). See
Section 11.1.1, “Offset 04 - 05h: Command Register”
The ADE is not sleeping due to the detection of an empty schedule. There is not one
single bit that indicates this state. However, the sleeping state is entered when the
Queue Head with the H bit set is encountered when the Reclamation bit in the USB
EHCI Status register is 0. See
USB EHCI STS—USB EHCI Status”
Memory
Section 11.2.2.2, “Offset CAPLENGTH + 04 - 07h: USB EHCI STS—USB
for more information.
Size (DW)
Up to 129
13
17
Only the 64-bit addressing format is supported.
Only the 64-bit addressing format is supported.
The Intel
down into smaller aligned read requests based on the
setting of the Read Request Max Length field.
Section 11.2.2.2, “Offset CAPLENGTH + 04 - 07h:
for information regarding offset 04h, bit 13.
®
6300ESB ICH breaks large read requests
Comments
for more information.
Order Number: 300641-004US
Intel
®
6300ESB ICH—5
November 2007