NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 24

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

15
16
Intel
DS
24
®
6300ESB I/O Controller Hub
14.2
Multimedia Timer Registers ................................................................................... 605
15.1
Watchdog Timer (WDT) (D29:F4) .......................................................................... 615
16.1
16.2
16.3
16.4
16.5
14.1.17Offset 50h: PID—PCI Power Management Capability ID Register (Modem—
14.1.18Offset 52h: PC—Power Management Capabilities Register (Modem—D31:F6) 591
14.1.19Offset 54h: PCS—Power Management Control and Status Register (Modem—
AC’97 Modem I/O Space (D31:F6) ..................................................................... 593
14.2.1 x_BDBAR—Buffer Descriptor List Base Address Register ............................. 595
14.2.2 x_CIV—Current Index Value Register ...................................................... 595
14.2.3 x_LVI—Last Valid Index Register............................................................. 596
14.2.4 x_SR—Status Register........................................................................... 596
14.2.5 x_PICB—Position in Current Buffer Register.............................................. 597
14.2.6 x_PIV—Prefetch Index Value Register ...................................................... 599
14.2.7 x_CR—Control Register.......................................................................... 599
14.2.8 GLOB_CNT—Global Control Register ........................................................ 600
14.2.9 GLOB_STA—Global Status Register ......................................................... 601
14.2.10CAS—Codec Access Semaphore Register.................................................. 604
Memory Mapped Registers ................................................................................ 605
15.1.1 Behavioral Rules ................................................................................... 605
15.1.2 Offset 000-007h: General Capabilities and ID Register............................... 606
15.1.3 Offset 010-017h: General Config Register ................................................ 607
15.1.4 Offset 020-027h: General Interrupt Status Register................................... 608
15.1.5 Offset 0F0 - 0f7h: Main Counter Value ..................................................... 609
15.1.6 Timer n Config and Capabilities............................................................... 609
15.1.7 Timer n Comparator Value ..................................................................... 613
Product Features ............................................................................................. 615
Product Overview ............................................................................................ 616
Signal Descriptions .......................................................................................... 617
Device 29: Function 4 Configuration Registers ..................................................... 617
16.4.1 Configuration Registers ......................................................................... 617
16.4.2 Memory Mapped Registers ..................................................................... 618
16.4.3 Offset 00h: VID—Vendor Identification Register ........................................ 618
16.4.4 Offset 02h: DID—Device Identification Register ........................................ 619
16.4.5 Offset 04 - 05h: COM—Command Register ............................................... 619
16.4.6 Offset 06h - 07h: DS—Device Status Register........................................... 620
16.4.7 Offset 08h: RID—Revision Identification Register ...................................... 621
16.4.8 Offset 09h: PI—Programming Interface Register ....................................... 622
16.4.9 Offset 0Ah: SCC—Sub Class Code Register............................................... 622
16.4.10Offset 0Bh: BCC—Base Code Class Register.............................................. 622
16.4.11Offset 0Eh: HEDT—Header Type Register ................................................. 622
16.4.12Offset 10h: BAR—Base Address Register .................................................. 623
16.4.13Offset 2Dh - 2Ch: SVID—Subsystem Vendor ID ........................................ 623
16.4.14Offset 2Eh - 2Fh: SID—Subsystem ID...................................................... 624
16.4.15Offset 60 - 61h: WDT Configuration Register ............................................ 625
16.4.16Offset 68h: WDT Lock Register ............................................................... 625
16.4.17Offset F8 - FBh: Manufacturer’s ID .......................................................... 627
16.4.18Offset Base + 00h: Preload Value 1 Register ............................................ 627
16.4.19Offset Base + 04h: Preload Value 2 Register ............................................ 628
16.4.20Offset Base + 08h: General Interrupt Status Register ................................ 628
16.4.21Offset Base + 0Ch: Reload Register......................................................... 629
Theory Of Operation......................................................................................... 629
16.5.1 RTC Well and WDT_TOUT# Functionality.................................................. 629
16.5.2 Register Unlocking Sequence.................................................................. 629
D31:F6)590
D31:F6)591
Intel
Order Number: 300641-004US
®
6300ESB ICH—Contents
November 2007