NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 284

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

Table 145. Memory Decode Ranges from CPU Perspective (Sheet 2 of 2)
Intel
DS
284
®
6300ESB I/O Controller Hub
512B anywhere in 4 Gbyte
range
256B anywhere in 4 Gbyte
range
1 Kbyte anywhere in 4
Gbyte range
FED0 X000 - FED0 X3FF
Gbyte range
1 Kbyte anywhere in 4
Gbyte range
1 Mbyte to 4 Gbyte
anywhere in 4 Gbyte range
All other
NOTES:
1. These ranges are decoded directly from Hub Interface. The memory cycles will not be seen on
2. Software must not attempt locks to memory mapped I/O ranges for USB EHCI, High
1 Kbyte anywhere in 4
FF70 0000 - FF7F FFFF
FF30 0000 - FF3F FFFF
FF60 0000 - FF6F FFFF
FF20 0000 - FF2F FFFF
FF50 0000 - FF5F FFFF
FF10 0000 - FF1F FFFF
FF40 0000 - FF4F FFFF
FF00 0000 - FF0F FFFF
PCI.
Performance Event Timers, and IDE Expansion. When attempted, the lock is not honored,
which means potential deadlock conditions may occur.
1 Kbyte anywhere
in 4 Gbyte range
Memory Range
AC’97 Host
Controller
(Mixer)
AC’97 Host
Controller
(Bus Master)
USB EHCI
Controller
Multimedia
Timers
SATA
WDT
PCI-X
PCI
Expansion
Target
FWH
FWH
FWH
FWH
1
IDE
1
1,
1
2
1,
2
2
1
Bit 3 in FWH Decode Enable 2 Register is set
Bit 2 in FWH Decode Enable 2 Register is set
Bit 1 in FWH Decode Enable 2 Register is set
Bit 0 in FWH Decode Enable 2 Register is set
Enable through standard PCI mechanism and bits
in IDE I/O Configuration Register (Device 31,
Function 1)
Enable via standard PCI mechanism (Device 31,
Function 5)
Enable via standard PCI mechanism (Device 31,
Function 5)
Enable through standard PCI mechanism (Device
29, Function 7).
BIOS determines the “fixed” location which is one
of four, 1-Kbyte ranges where X (in the first
column) is 0h, 1h, 2h, or 3h.
Enable via standard PCI mechanism (Device 31,
Function 2)
Enable via standard PCI mechanism (Device 29,
Function 4)
Enable via standard PCI mechanism (Device 28,
Function 0)
None/ If the address is below 16M, is not in one of
the above BIOS Ranges, and positive decode is
disabled; then the cycle will be forwarded to LPC
as a standard LPC memory cycle.
If the address is above 16M, if the cycle is not
claimed by a device on PCI and neither by the
Intel
Abort on PCI
®
6300ESB ICH, then the cycle will Master-
Dependency/Comments
Order Number: 300641-004US
Intel
®
6300ESB ICH—6
November 2007