NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 225

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

5—Intel
5.18.4.1.2 Write Policies for Periodic DMA
Table 110. Write Policies for Periodic DMA
November 2007
Order Number: 300641-004US
®
Note: Prefetching is limited to the current and next microframes only.
Note: Once the PDE checks the length of a periodic packet against the remaining time in the
6300ESB ICH
The EHC Periodic DMA Engine (PDE) does not generate accesses to main memory
unless all three of the following conditions are met.
microframe (late-start check) and decides that there is not enough time to run it on the
wire, then the EHC switches over to run asynchronous traffic.
The Periodic DMA engine performs writes for the following reasons.
iTD Status Write
siTD Status Write
Interrupt Queue Head
Overlay
Interrupt Queue Head
Status Write
Interrupt qTD Status
Write
In Data
NOTES:
•
•
•
1. The Periodic DMA Engine (PDE) will only generate writes after a transaction is executed on
2. Status writes are always performed after In Data writes for the same transaction.
Memory Structure
USB.
The HCHalted bit is 0 (memory space, offset 04h, bit 12). Software clears this bit
indirectly by setting the RUN/STOP bit to 1. See
CAPLENGTH + 04 - 07h: USB EHCI STS—USB EHCI Status”
The Periodic Schedule Status bit is 1 (memory space, offset 04h, bit 14). Software
sets this bit indirectly by setting the Periodic Schedule Enable Bit to 1. See
Section 11.2.2.2, “Offset CAPLENGTH + 04 - 07h: USB EHCI STS—USB EHCI
Status”
The Bus Master Enable bit is 1 (configuration space, offset 04h, bit 2). See
Section 11.1.1, “Offset 04 - 05h: Command Register”
for more information.
(DWORDs
Up to 257
Size
14
1
3
5
3
)
Only the DWORD that corresponds to the just-
executed microframe’s status is written. All bytes of
the DWORD are written.
DWORDs 0C:17h are written. IOC and Buffer Pointer
fields are re-written with the original value.
Only the 64-bit addressing format is supported.
DWORDs 0C:43h are written.
DWORDs 14:27h are written.
DWORDs 04:0Fh are written. PID Code, IOC, Buffer
Pointers, and Alt. Next qTD Pointers are re-written
with the original value.
The Intel
16 DWORD aligned chunks.
®
6300ESB ICH breaks data writes down into
Section 11.2.2.2, “Offset
Comments
for more information.
Intel
®
for more information.
6300ESB I/O Controller Hub
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