NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 610

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

Intel
DS
610
64:5
6
63:3
2
31:1
6
15
14
Offset:
Bits
Default Value:
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Table 533. Timer n Config and Capabilities (Sheet 1 of 3)
6300ESB I/O Controller Hub
TIMERn_INT_ROUT_CAP
TIMERn_FSB_INT_DEL_
TIMERn_INT_ROUT[31:
TIMERn_FSB_EN_CNF
CAP: FSB Interrupt
Reserved
Reserved
Delivery
0]_CAP
Timer 0: 100-107h,
Timer 1: 120-127h,
Timer 2: 140-147h
N/A
Name
:
Reserved. These bits will return ’0’ when read.
This 32-bit read-only field indicates which interrupts in the I/
O (x) APIC this timer’s interrupt may be routed to. This is
used in conjunction with the TIMERn_INT_ROUT_CNF field.
Each bit in this field corresponds to a particular interrupt. For
example, when this timer’s interrupt may be mapped to
interrupts 16, 18, 20, 22, or 24, bits 16, 18, 20, 22, and 24 in
this field will be set to ‘1’. All other bits will be ‘0’.
Intel
and 23 in this field (corresponding to bits 52, 53, 54, and 55
in this register) will have a value of ‘1’. All other bits will be
‘0’. Writes will have no effect.
Intel
22, and 23 in this field (corresponding to bits 43, 52, 53, 54,
and 55 in this register) will have a value of ‘1’. All other bits
will be ‘0’. Writes will have no effect. When IRQ 11 is used for
MMT#2, software should ensure IRQ11 is not shared with any
other devices to ensure the proper operation of MMT#2.
Reserved. These bits will return ’0’ when read.
(where n is the timer number: 00 to 31)
If this read-only bit is 1, then the hardware supports a direct
processor side bus delivery of this timer’s interrupt.
NOTE: This bit will always read as 0, since the Intel
(where n is the timer number: 00 to 31).
If the TIMERn_FSB_INT_DEL_CAP bit is set for this timer,
then the software can set the TIMERn_FSB_EN_CNF bit to
force the interrupts to be delivered directly as FSB messages,
rather than using the I/O (x) APIC. In this case, the
TIMERn_INT_ROUT_CNF field in this register will be ignored.
The TIMERn_FSB_ROUT register will be used instead.
®
®
6300ESB ICH and Timer 0, 1 Specific: Bits 20, 21, 22,
6300ESB ICH and Timer 2 Specific: Bits 11, 20, 21,
6300ESB ICH Multimedia Timer implementation does
not support the direct FSB interrupt delivery.
Description
Attribute:
Size:
Read/Write
64-bit
Order Number: 300641-004US
®
Intel
®
6300ESB ICH—15
November 2007
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