NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 155

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

5—Intel
5.11.7
5.11.7.1 Sleep State Overview
5.11.7.2 Initiating Sleep State
November 2007
Order Number: 300641-004US
®
6300ESB ICH
Other Implementation Notes:
Exception: For SMI#s that are caused by a processor I/O cycle, when STPCLK# is
active, the Intel
STPCLK# was obviously too late to be recognized at the instruction boundary. The I/O
cycles that may cause SMI# include: writes to the APM register (B2h), accesses to 60/
64h when “Legacy USB KBC scheme” is used, traps for Monitors 4, 5, 6, and 7, the
SMI# on SLP_EN bit, accesses to 62/66h when the MCSMI_EN bit is set, access to
registers with their associated enable set in the DEVTRAP_EN register, and the
BIOS_STS bit (which is set by the processor writing a 1 to the GLB_RLS bit when the
BIOS_EN bit is also set).
Sleep States
The Intel
entered by setting the SLP_EN bit, or due to a Power Button press. The entry to the
Sleep states are based on several assumptions:
Sleep states (S1–S5) are initiated by:
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When STPCLK# goes active due to a Level read, it must go active prior to the
completion of the associated I/O read. This is to ensure that the STPCLK# is
recognized by the processor prior to it recognizing the end of the I/O cycle. That
will prevent the next instruction from being executed.
The state machine must insure that the STPCLK# signal stays high for a minimum
period of time. When STPCLK# is to go low due to throttling (regular or due to the
THRM# signal), this could be very soon after it was driven high. The MCH should
ensure that the Stop-Grant cycle coming down the Hub Interface occurs after the
BRDY# is seen by the processor.
Entry to a Cx state is mutually exclusive with entry to a Sleep state. This is because
the processor may only perform one register access at a time. A request to Sleep
always has higher priority than throttling.
Prior to setting the SLP_EN bit, the software will turn off processor-controlled
throttling. Note that thermal throttling cannot be disabled, but setting the SLP_EN
bit will disable thermal throttling (since S1–S5 sleep state has higher priority).
The G3 state cannot be entered through any software mechanism. The G3 state
indicates a complete loss of power.
Masking interrupts, turning off all bus master enable bits, setting the desired type
in the SLP_TYP field and then setting the SLP_EN bit. The hardware will then
attempt to gracefully put the system into the corresponding Sleep state by first
going to a C2 state. See
details on going to the C2 state.
Pressing the PWRBTN# Signal for more than four seconds to cause a Power Button
Override event. In this case the transition to the S5 state will be less graceful, since
there will be no dependencies on observing Stop-Grant cycles from the processor
or on clocks other than the RTC clock.
®
6300ESB ICH directly supports different sleep states (S1–S5), which are
®
6300ESB ICH will still drive SMI# active. This is because the
Section 5.11.6, “Dynamic Processor Clock Control”
Intel
®
6300ESB I/O Controller Hub
for
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