NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 811
NHE6300ESB S L7XJ
Manufacturer Part Number
NHE6300ESB S L7XJ
Description
Manufacturer
Intel
Datasheet
1.NHE6300ESB_S_L7XJ.pdf
(848 pages)
Specifications of NHE6300ESB S L7XJ
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22—Intel
Table 727. Power Sequencing and Reset Signal Timings
November 2007
Order Number: 300641-004US
NOTES:
1. The V5Ref supply must power up before or simultaneous with its associated 3.3 V supply, and must power
2. The associated 3.3 V and 1.5 V supplies must power up or down simultaneously.
3. The VccSus supplies must never be active while the VccRTC supply is inactive.
4. SYSRESET# is not checked for PWROK transitions (t177).
Sym
t170
t171
t172
t173
t174
t175
t176
t177
t178
t179
t180
down simultaneous with or after the 3.3 V supply. See the Intel
®
VccRTC active to RTCRST# inactive
V5RefSus active to VccSus3_3, VccSus1_5 active
VccRTC supply active to VccSus supplies active
VccSus supplies active to RSMRST# inactive
V5Ref active to Vcc3_3, Vcc1_5, VccHI active
VccSus supplies active to Vcc3_3, Vcc1_5, VccHI
supplies active
Vcc3_3, Vcc1_5, VccHI supplies active to PWROK.
PWROK active to SUS_STAT# inactive
SUS_STAT# inactive to PXPCIRST# inactive
AC_RST# active low pulse width
AC_RST# inactive to BIT_CLK startup delay
6300ESB ICH
Parameter
162.8
Min
®
10
99
32
5
0
0
0
0
1
1
6300ESB ICH Design Guide for details.
Max
38
3
-
-
-
-
-
-
-
Intel
RTCCLK
RTCCLK
Units
ms
ms
ms
ms
ms
ms
ms
us
ns
®
6300ESB I/O Controller Hub
Notes
1,
1,
3
3
4
2
2
Figure 61
Figure 61
Figure 61
Figure 61
Figure 62
Figure 61
Figure 61
Figure 61
Figure 62
Figure 64
Figure 62
Figure 64
Figure 62
Figure 64
Fig
811
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