NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 647

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

18—Intel
PCI-X Overview (D28:F0)
18.1
November 2007
Order Number: 300641-004US
Note: Since the Intel
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6300ESB ICH
notation PCI-X will be used to refer to the PCI-X interface. Since the PCI-X interface can
support the PCI-X protocol as well as the PCI protocol, the PCI-X terminology is
intended to refer to the interface being described and not to the protocol.
I/O Window Addressing
This section describes the I/O window that may be set up in the bridge. Refer to
Section 18.3, “VGA Addressing”
The register bits listed below also modify the response by the Intel
O transactions:
To enable outbound I/O transactions, the I/O enable bit must be set in the command
register in the Intel
the I/O enable bit is not set, all I/O transactions initiated on the Hub Interface receive a
master abort completion. No inbound I/O transactions may cross the bridge and are
therefore master aborted.
The Intel
configuration space that define an I/O address range for the bridge. Hub interface I/O
transactions with addresses that fall inside the range defined by the I/O base and limit
registers are forwarded to PCI-X, and PCI-X I/O transactions with addresses that fall
outside this range are master aborted.
Setting the base address to a value greater than that of the limit address turns off the
I/O range. When the I/O range is turned off, no I/O transactions are forwarded to PCI
even when the I/O enable bit is set. The I/O range has a minimum granularity of 4
Kbytes and is aligned on a 4 Kbyte boundary. The maximum I/O range is 64 Kbytes.
This range may be lowered to 1K granularity by setting the EN1K bit in the Intel
6300ESB ICH Configuration register at offset 40h.
The base register consists of an 8-bit field at configuration address 1Ch, and a 16-bit
field at address 30h. The top four bits of the 8-bit field define bits [15:12] of the I/O
base address. The bottom four bits read only as 0h to indicate that the Intel
ICH supports 16-bit I/O addressing. Bits [11:0] of the base address are assumed to be
’0’, which naturally aligns the base address to a 4 Kbyte boundary. The I/O base upper
16 bits register at offset 30h is reserved. After chip reset, the value of the I/O base
address is initialized to 0000h.
The I/O limit register consists of an 8-bit field at offset 1Dh and a 16-bit field at offset
32h. The top four bits of the 8-bit field define bits [15:12] of the I/O limit address. The
bottom four bits read only as 0h to indicate that 16-bit I/O addressing is supported.
Bits [11:0] of the limit address are assumed to be FFFh, which naturally aligns the limit
address to the top of a 4 Kbyte I/O address block. The 16 bits contained in the I/O limit
upper 16 bits register at offset 32h are reserved. After chip reset, the value of the I/O
limit address is reset to 0FFFh.
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•
•
•
I/O Base and Limit Registers
I/O Enable bit in the Command Register
Master enable bit in the Command Register
Enable 1K granularity in the Intel
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6300ESB ICH implements one set of I/O base and limit address registers in
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6300ESB ICH supports a PCI interface and a PCI-X interface, the
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6300ESB ICH configuration space (bit ’0’ at offset 04-05h). When
to see how I/O cycles in the VGA range are handled.
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6300ESB ICH Configuration Register
Intel
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6300ESB I/O Controller Hub
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6300ESB ICH to I/
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6300ESB
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