NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 406

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

Table 292. SMI_EN—SMI Control and Enable Register (Sheet 2 of 3)
Intel
DS
406
10:8
Bits
Default Value:
14
13
12
11
I/O Address:
7
6
5
4
3
®
6300ESB I/O Controller Hub
Lockable:
Device:
MCSMI_EN: Microcon-
Software SMI# Timer
troller SMI Enable
SWSMI_TMR_EN:
LEGACY_USB_EN
BIOS_RLS: BIOS
PERIODIC_EN
SLP_SMI_EN
APMC_EN
Reserved
Reserved
TCO_EN
Release
Enable
31
PMBASE + 30h
00000000h
No
Name
0 = Disable.
1 = Enables the Intel
0 = Disables TCO logic generating an SMI#. Note that when
1 = Enables the TCO logic to generate SMI#.
NOTE: This bit can not be written once the TCO_LOCK bit (at
Reserved.
0 = Disable.
1 = Enables the Intel
Reserved.
0 = This bit will always return 0 on reads. Writes of 0 to this
1 = Enables the generation of an SCI interrupt for ACPI
0 = Disable. Clearing the SWSMI_TMR_EN bit before the
1 = Starts Software SMI# Timer. When the SWSMI timer
0 = Disable. Writes to the APM_CNT register will not cause an
1 = Enables writes to the APM_CNT register to cause an
0 = Disables the generation of SMI# on SLP_EN. Note that
1 = A write of 1 to the SLP_EN bit (bit 13 in PM1_CNT
0 = Disable.
1 = Enables legacy USB circuit to cause SMI#.
when the PERIODIC_STS bit is set in the SMI_STS
register.
the NMI2SMI_EN bit is set, SMIs that are caused by re-
routed NMIs will not be gated by the TCO_EN bit. Even
when the TCO_EN bit is 0, NMIs will still be routed to
cause SMIs.
microcontroller range (62h or 66h) and generate an
SMI#. Note that “trapped’ cycles will be claimed by the
Intel
bit have no effect.
software when a one is written to this bit position by
BIOS software.
timer expires will reset the timer and the SMI# will not
be generated.
expires (the timeout period depends upon the
SWSMI_RATE_SEL bit setting), SWSMI_TMR_STS is set
and an SMI# is generated. SWSMI_TMR_EN stays set
until cleared by software.
SMI#.
SMI#.
this bit must be 0 before the software attempts to
transition the system into a sleep state by writing a 1 to
the SLP_EN bit.
register) will generate an SMI#, and the system will not
transition to the sleep state based on that write to the
SLP_EN bit.
offset 08h of TCO I/O Space) is set. This prevents
unauthorized software from disabling the generation
of TCO-based SMI’s
®
6300ESB ICH on PCI, but not forwarded to LPC.
®
®
6300ESB ICH to generate an SMI#
6300ESB ICH to trap accesses to the
Power Well:
Description
Attribute:
Function:
Size:
0
Read/Write
32-bit
Core
Order Number: 300641-004US
Intel
®
6300ESB ICH—8
November 2007
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
WO