NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 37

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

Contents—Intel
November 2007
Order Number: 300641-004US
216 Offset F2h: FUNC_DIS—Function Disable Register (LPC I/F—D31:F0) ............................ 343
217 Offset F4: ETR1—PCI-X Extended Features Register (LPC I/F—D31:F0) ......................... 345
218
219 DMABASE_CA—DMA Base and Current Address Registers ............................................ 346
220 DMABASE_CA—DMA Base and Current Address Registers ............................................ 348
221 DMABASE_CC—DMA Base and Current Count Registers ............................................... 349
222 DMABASE_CC—DMA Base and Current Count Registers ............................................... 350
223 DMACMD—DMA Command Register .......................................................................... 350
224 DMASTA—DMA Status Register ................................................................................ 351
225 DMA_WRSMSK—DMA Write Single Mask Register ....................................................... 352
226 DMACH_MODE—DMA Channel Mode Register ............................................................. 352
227 DMA Clear Byte Pointer Register .............................................................................. 353
228 DMA Master Clear Register ...................................................................................... 354
229 DMA_CLMSK—DMA Clear Mask Register .................................................................... 354
230 DMA_WRMSK—DMA Write All Mask Register .............................................................. 355
231 Timer I/O Registers ................................................................................................ 355
232 TCW —Timer Control Word Register.......................................................................... 356
233 RDBK_CMD—Read Back Command ........................................................................... 357
234 LTCH_CMD—Counter Latch Command....................................................................... 358
235 SBYTE_FMT—Interval Timer Status Byte Format Register ............................................ 359
236 Counter Access Ports Register.................................................................................. 360
237 PIC Registers......................................................................................................... 360
238 ICW1—Initialization Command Word 1 Register.......................................................... 361
239 ICW2—Initialization Command Word 2 Register.......................................................... 362
240 ICW3—Master Controller Initialization Command Word 3 Register ................................. 363
241 ICW3—Slave Controller Initialization Command Word 3 Register .................................. 363
242 ICW4—Initialization Command Word 4 Register.......................................................... 364
243 OCW1—Operational Control Word 1 (Interrupt Mask) Register...................................... 364
244 OCW2—Operational Control Word 2 Register.............................................................. 365
245 OCW3—Operational Control Word 3 Register.............................................................. 366
246 ELCR1—Master Controller Edge/Level Triggered Register ............................................. 367
247 ELCR2—Slave Controller Edge/Level Triggered Register............................................... 367
248 APIC Direct Registers.............................................................................................. 368
249 APIC Indirect Registers ........................................................................................... 369
250 IND—Index Register ............................................................................................... 369
251 DAT—Data Register ................................................................................................ 370
252 Offset FEC0_0020h: IRQPA—IRQ Pin Assertion Register .............................................. 370
253 Offset FEC0 - EOIR: EOI Register ............................................................................. 371
254 Offset 00h: ID—Identification Register ...................................................................... 371
255 Offset 01h: VER—Version Register............................................................................ 372
256 Offset 02h: ARBID—Arbitration ID Register ............................................................... 372
257 Offset 02h: ARBID—Arbitration ID Register ............................................................... 373
258 Offset 10h - 11h (Vector 0) through 3E - 3Fh (Vector 23): Redirection Table.................. 373
259 Delivery Mode Encoding .......................................................................................... 375
260 RTC I/O Registers .................................................................................................. 376
261 RTC (Standard) RAM Bank....................................................................................... 376
262 RTC_REGD—Register D (Flag Register) ..................................................................... 377
263 RTC_REGB—Register B (General Configuration) ......................................................... 378
264 RTC_REGC—Register C (Flag Register)...................................................................... 380
265 RTC_REGD—Register D (Flag Register) ..................................................................... 380
266 NMI_SC—NMI Status and Control Register................................................................. 381
267 NMI_EN—NMI Enable (and Real Time Clock Index) ..................................................... 382
268 PORT92—Fast A20 and Init Register ......................................................................... 382
269 COPROC_ERR—Coprocessor Error Register ................................................................ 383
270 RST_CNT—Reset Control Register ............................................................................ 383
Offset F8h: Manufacturer’s ID
®
6300ESB ICH
.................................................................................. 345
Intel
®
6300ESB I/O Controller Hub
DS
37