NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 419

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

8—Intel
8.9.6
Table 306. TCO1_STS—TCO1 Status Register (Sheet 1 of 2)
November 2007
Order Number: 300641-004US
15:1
Bits
Default Value:
12
11
10
I/O Address:
3
9
8
Lockable:
®
Device:
6300ESB ICH
HUBSERR_STS
BIOSWR_STS
HUBNMI_STS
HUBSMI_STS
HUBSCI_STS
TCO1_STS—TCO1 Status Register
Reserved
31
TCOBASE +04h
0000h
No
Name
Reserved.
0 = Software clears this bit by writing a 1 to the bit position.
1 = The Intel
NOTE: When this bit is set AND the SERR_EN bit in CMD
0 = Software clears this bit by writing a 1 to the bit position.
1 = The Intel
0 = Software clears this bit by writing a 1 to the bit position.
1 = The Intel
0 = Software clears this bit by writing a 1 to the bit position.
1 = The Intel
0 = Software clears this bit by writing a 1 to the bit position.
1 = The Intel
through the Hub Interface. The software must read the
memory controller hub (or its equivalent) to determine
the reason for the SERR#.
through the Hub Interface. The software must read the
memory controller hub (or its equivalent) to determine
the reason for the NMI.
through the Hub Interface. The software must read the
memory controller hub (or its equivalent) to determine
the reason for the SMI#.
through the Hub Interface. The software must read the
memory controller hub (or its equivalent) to determine
the reason for the SCI.
SMI# to indicate an illegal attempt to write to the BIOS.
This occurs when either:
a) The BIOSWP bit is changed from 0 to 1 and the BLD bit
is also set, or
b) any write is attempted to the BIOS and the BIOSWP
bit is also set.
register (D30:F0, Offset 04h, bit 8) is also set, the
Intel
register (D30:F0, offset 1Eh, bit 14) AND will also
generate a NMI (or SMI# when NMI routed to SMI#).
®
®
®
®
®
®
6300ESB ICH will set the SSE bit in SECSTS
6300ESB ICH received an SERR# message
6300ESB ICH received an NMI message
6300ESB ICH received an SMI message
6300ESB ICH received an SCI message
6300ESB ICH sets this bit and generates and
Power Well:
Description
Attribute:
Function:
Size:
0
Read-Only, Read/Write Clear
16-bit
Core (Except bit 7, in RTC)
Intel
®
6300ESB I/O Controller Hub
Access
R/WC
R/WC
R/WC
R/WC
R/WC
419
DS