NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 296

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

Table 162. Offset 1E - 1Fh: SECSTS—Secondary Status Register (HUB-PCI—
7.1.17
Intel
DS
296
Bits
Default Value:
3:0
8
7
6
5
4
®
6300ESB I/O Controller Hub
Device:
Master Data Parity Error
User Definable Features
PERR# Assertion Detect
Offset:
Fast Back to Back
Detected (MDPD)
66 MHz Capable
D30:F0)
Offset 20 - 21h: MEMBASE—Memory Base Register
(HUB-PCI—D30:F0)
This register defines the base of the Hub Interface to PCI non-prefetchable memory
range. Since the Intel
to PCI, the Intel
to accept cycles as a target.
This register must be initialized by the configuration software. For the purpose of
address decode, address bits AD[19:0] are assumed to be zero. Thus, the bottom of
the defined memory address range will be aligned to a 1 Mbyte boundary.
Reserved
30
1E-1Fh
0280h
Name
(UDF)
®
0 = Software clears this bit by writing a’1’ to the bit position.
1 = The Intel
Hardwired to ‘1’ to indicate that the PCI to Hub Interface
target logic is capable of receiving fast back-to-back cycles.
Hardwired to ‘0’.
Hardwired to ‘0’.
This bit is set by hardware whenever the PERR# pin is
asserted on the rising edge of PCI clock. This includes cases
in which the chipset is the agent driving PERR#. It remains
asserted until cleared by software writing a ‘1’ to this
location. When enabled by the PERR#-to-SERR# Enable bit
(in the Bridge Control register), a ‘1’ in this bit can generate
an internal SERR# and be a source for the NMI logic.
Reserved.
6300ESB ICH will only use this information for determining when not
- The Parity Error Response Enable bit in the Bridge
Control Register (bit 0, offset 3Eh) is set
- USB, AC’97 or IDE is a Master
- PERR# asserts during a write cycle OR a parity error is
detected internally during a read cycle
following three conditions are met:
®
6300ESB ICH will forward all Hub Interface memory accesses
®
6300ESB ICH sets this bit when all of the
Description
Attribute:
Function:
Size:
0
Read/Write
16-bit
Order Number: 300641-004US
Intel
®
6300ESB ICH—7
November 2007
Access
R/WC
R/WC
RO
RO
RO