NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 116

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

5.6.2.1
5.6.2.2
5.6.2.3
5.6.2.4
5.6.3
Intel
DS
116
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6300ESB I/O Controller Hub
The base address for each 8259 initialization command word is a fixed location in the I/
O memory space: 20h for the master controller, and A0h for the slave controller.
ICW1
An I/O write to the master or slave controller base address with data bit 4 equal to 1 is
interpreted as a write to ICW1. Upon sensing this write, the Intel
expects three more byte writes to 21h for the master controller, or A1h for the slave
controller, to complete the ICW sequence.
A write to ICW1 starts the initialization sequence during which the following
automatically occur:
ICW2
The second write in the sequence, ICW2, is programmed to provide bits [7:3] of the
interrupt vector that will be released during an interrupt acknowledge. A different base
is selected for each interrupt controller.
ICW3
The third write in the sequence, ICW3, has a different meaning for each controller.
ICW4
The final write in the sequence, ICW4, must be programmed both controllers. At the
very least, bit 0 must be set to one to indicate that the controllers are operating in an
Intel
Operation Command Words (OCW)
These command words reprogram the Interrupt Controller to operate in various
interrupt modes.
1. Following initialization, an interrupt request (IRQ) input must make a low-to-high
2. The Interrupt Mask Register is cleared.
3. IRQ7 input is assigned priority 7.
4. The slave mode address is set to 7.
5. Special mask mode is cleared and Status Read is set to IRR.
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transition to generate an interrupt.
For the master controller, ICW3 is used to indicate which IRQ input line is used to
cascade the slave controller. Within the Intel
Therefore, bit 2 of ICW3 on the master controller is set to a 1, and the other bits
are set to 0s.
For the slave controller, ICW3 is the slave identification code used during an
interrupt acknowledge cycle. On interrupt acknowledge cycles, the master
controller broadcasts a code to the slave controller when the cascaded interrupt
won arbitration on the master controller. The slave controller compares this
identification code to the value stored in its ICW3, and when it matches, the slave
controller assumes responsibility for broadcasting the interrupt vector.
OCW1 masks and unmasks interrupt lines.
OCW2 controls the rotation of interrupt priorities when in rotating priority mode,
and controls the EOI function.
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Architecture-based system.
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6300ESB ICH, IRQ2 is used.
Order Number: 300641-004US
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Intel
6300ESB ICH PIC
®
6300ESB ICH—5
November 2007