NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 46

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

Intel
DS
46
697 Offset Index 54h - 57h: SER0—SATA SError Register Port 0 (SATA–D31:F2) .................. 763
698 Offset Index 64h - 67h: SER1—SATA SError Register Port 1 (SATA–D31:F2) .................. 763
699 Offset E0h - E3h: BFCS—BIST FIS Control/Status Register (SATA–D31:F2) .................... 763
700 Offset E4h - E7h: BFTD1—BIST FIS Transmit Data1 Register (SATA–D31:F2) ................. 765
701 Offset E8h - EBh: BFTD2—BIST FIS Transmit Data2 Register (SATA–D31:F2) ................. 766
702 Bus Master IDE I/O Registers ................................................................................... 766
703 BMIC[P,S]—Bus Master IDE Command Register (D31:F2) ............................................ 767
704 BMIS[P,S]—Bus Master IDE Status Register (D31:F2) ................................................. 768
705 BMID[P,S]—Bus Master IDE Descriptor Table Pointer Register (D31:F2)......................... 769
706 Signal List (Alphabetical List) ................................................................................... 774
707 Signal List (by Location) .......................................................................................... 781
708 DC Current Characteristics (Preliminary).................................................................... 790
709 DC Characteristic Input Signal Association ................................................................. 790
710 DC Input Characteristics .......................................................................................... 791
711 DC Characteristic Output Signal Association ............................................................... 793
712 DC Output Characteristics........................................................................................ 794
713 Other DC Characteristics ......................................................................................... 794
714 Clock Timings ........................................................................................................ 796
715 PCI-X Interface Timings .......................................................................................... 799
716 PCI Interface Timing ............................................................................................... 800
717 IDE PIO and Multiword DMA ModeTiming ................................................................... 801
718 Ultra ATA Timing (Mode 0, Mode 1, Mode 2)............................................................... 802
719 Ultra ATA Timing (Mode 3, Mode 4, Mode 5)............................................................... 804
720 Universal Serial Bus Timing...................................................................................... 806
721 SATA Interface Timings ........................................................................................... 808
722 SMBus Timing ........................................................................................................ 808
723 AC’97 Timing ......................................................................................................... 809
724 LPC Timing ............................................................................................................ 809
725 Miscellaneous Timings ............................................................................................. 809
726 UART Timings ........................................................................................................ 810
727 Power Sequencing and Reset Signal Timings .............................................................. 811
728 Power Management Timings..................................................................................... 812
729 Clock Uncertainty Parameters .................................................................................. 813
730 PCI-X Measurement Condition Parameters ................................................................. 815
731 Test Mode Selection................................................................................................ 825
732 XOR Test Pattern Example ....................................................................................... 827
733 XOR Chain #1 (RTCRST# asserted for 4 PCI clocks
734 XOR Chain #2 (RTCRST# asserted for 5 PCI clocks
735 XOR Chain #3 (RTCRST# asserted for 6 PCI clocks
736 XOR Chain #4 (RTCRST# asserted for 7 PCI clocks
737 XOR Chain #5 (RTCRST# asserted for 59 PCI clocks
738 XOR Chain #6 (RTCRST# asserted for 52 PCI clocks while PWROK active)...................... 834
739 XOR Chain #7 (RTCRST# asserted for 60 PCI clocks while PWROK active)...................... 834
®
6300ESB I/O Controller Hub
while PWROK active)............................................................................................... 827
while PWROK active)............................................................................................... 828
while PWROK active)............................................................................................... 829
while PWROK active)............................................................................................... 831
while PWROK active)............................................................................................... 831
Intel
Order Number: 300641-004US
®
6300ESB ICH—Contents
November 2007