NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 378

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

8.6.2.2
Table 263. RTC_REGB—Register B (General Configuration)
Intel
DS
378
Bits
Default Value:
7
6
5
4
3
®
RTC Index:
6300ESB I/O Controller Hub
Lockable:
Device:
PIE: Periodic Interrupt
SQWE: Square Wave
AIE: Alarm Interrupt
UIE: Update-Ended
SET: Update Cycle
Interrupt Enable
RTC_REGB—Register B (General Configuration)
Inhibit
Enable
Enable
Enable
31
0Bh
U0U00UUU (U:
Undefined)
No
Name
Enables/Inhibits the update cycles. This bit is not affected by
RSMRST# nor any other reset signal.
0 = Update cycle occurs normally once each second.
1 = A current update cycle will abort and subsequent update
This bit is cleared by RSMRST#, but not on any other reset.
0 = Disable.
1 = Allows an interrupt to occur with a time base set with the
This bit is cleared by RSMRST#, but not on any other reset.
0 = Disable.
1 = Allows an interrupt to occur when the AF is set by an
This bit is cleared by RSMRST#, but not on any other reset.
0 = Disable.
1 = Allows an interrupt to occur when the update cycle ends.
This bit serves no function in the Intel
left in this register bank to provide compatibility with the
Motorola* 146818B. The Intel
pin. This bit is cleared by RSMRST#, but not on any other
reset.
cycles will not occur until SET is returned to zero. When
set is one, the BIOS may initialize time and calendar
bytes safely.
RS bits of register A.
alarm match from the update cycle. An alarm may occur
once a second, one an hour, once a day, or one a month.
Power Well:
Description
Attribute:
Function:
®
Size:
6300ESB ICH has no SQW
0
Read-Write
8-bit
RTC
®
6300ESB ICH. It is
Order Number: 300641-004US
Intel
®
6300ESB ICH—8
November 2007
Access
R/W
R/W
R/W
R/W
R/W