NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 622
NHE6300ESB S L7XJ
Manufacturer Part Number
NHE6300ESB S L7XJ
Description
Manufacturer
Intel
Datasheet
1.NHE6300ESB_S_L7XJ.pdf
(848 pages)
Specifications of NHE6300ESB S L7XJ
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16.4.8
Table 543. Offset 09h: PI—Programming Interface Register
16.4.9
Table 544. Offset 0Ah: SCC—Sub Class Code Register
16.4.10 Offset 0Bh: BCC—Base Code Class Register
Table 545. Offset 0Bh: BCC—Base Code Class Register
16.4.11 Offset 0Eh: HEDT—Header Type Register
Intel
DS
622
Bits
Bits
Bits
Default Value:
Default Value:
Default Value:
7:0
7:0
7:0
®
6300ESB I/O Controller Hub
Lockable:
Lockable:
Lockable:
Note: The Base Address Register points to several memory mapped registers for the
Device:
Device:
Device:
Offset:
Offset:
Offset:
Programming Interface
Base Code Class
Sub Class Code
Offset 09h: PI—Programming Interface Register
Offset 0Ah: SCC—Sub Class Code Register
Watchdog Timer. It decodes the smallest possible region of 16 Bytes.
29
09h
00h
No
Name
29
0Ah
80h
No
Name
29
0Bh
08h
No
Name
Power Well:
Power Well:
Power Well:
Description
Description
Description
Attribute:
Attribute:
Attribute:
Function:
Function:
Function:
Size:
Size:
Size:
4
Read-Only
8-bit
Core
4
Read-Only
8-bit
Core
4
Read-Only
8-bit
Core
Order Number: 300641-004US
Intel
®
6300ESB ICH—16
November 2007
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