NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 425
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NHE6300ESB S L7XJ
Manufacturer Part Number
NHE6300ESB S L7XJ
Description
Manufacturer
Intel
Datasheet
1.NHE6300ESB_S_L7XJ.pdf
(848 pages)
Specifications of NHE6300ESB S L7XJ
Lead Free Status / RoHS Status
Compliant
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8—Intel
8.10
8.10.1
Table 313. Registers to Control GPIO
November 2007
Order Number: 300641-004US
®
6300ESB ICH
General Purpose I/O Registers (D31:F0)
The control for the general purpose I/O signals is handled through a separate 64-byte
I/O space. The base offset for this space is selected by the GPIO_BAR register.
GPIO Register I/O Address Map
00-03h
04-07h
0C-0Fh
18-1Bh
2C-2Fh
30-33h
34-37h
38-3Bh
Offset
GPIO_USE_SEL
GPIO_USE_SEL
GP_IO_SEL2
GPO_BLINK
Mnemonic
GP_IO_SEL
GP_LVL2
GPI_INV
GP_LVL
2
GPIO Use Select
GPIO Input/Output Select
GPIO Level for Input or Output
GPIO Blink Enable
GPIO Signal Invert
GPIO Use Select
GPIO Input/Output Select 2
GPIO Level for Input or Output 2
Output Control Registers
Input Control Registers
General Registers
Register Name
Intel
®
6300ESB I/O Controller Hub
1B003100h
00000000h
00000000h
03000000h
00000000h
00000FFFh
Default
0000h
FFFFh
0000
1F1F
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
425
DS
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