NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 121

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

5—Intel
5.7
5.7.1
5.7.2
November 2007
Order Number: 300641-004US
®
6300ESB ICH
Advanced Interrupt Controller (APIC)
(D29:F5)
There are two APICs in the Intel
5). APIC0’s direct registers are assigned with base address FEC0xxxxH; however, only
primary (legacy) PCI devices can write to these registers. APIC1’s direct register are
assigned with base address FEC1xxxxH. To support legacy devices/drivers on the PCI-X
segment used with the Intel ICHx, APIC1 has an alternate base address FEC0xxxxH.
This means devices on the PCI-X segment can only write to the IRQ Pin Assertion
Register (either FEC0_0020H or FEC1_0020H) to generate an interrupt from APIC1.
APIC1 writes to addresses FEC1_0020 to FEC1_0027 are claimed by APIC1 from PCI-X.
Devices on the primary PCI Bus can write to IRQ Pin Assertion Register FEC0_0020H to
generate an APIC0 interrupt. Devices/drivers on the PCI-X segment have write access
only to the APIC1 IRQ Pin Assertion Register. Devices/drivers on the PCI segment can
access only APIC0 registers. Since the Intel
Interface EOI special cycles, the MCH will translate EOI special cycle to a memory write
cycle to EOI register at address FEC0_0040H and passes it to the Intel
This memory write cycle will be passed to both APIC0 and APIC1 internally.
From the CPU/MCH point of view, it should always use address FEC0xxxxH to access
APIC0 registers and address FEC1xxxxH to access APIC1 registers. APIC1 will not
respond to CPU/MCU’s access to address FEC0xxxxH, other than the EOI cycle stated
above.
Interrupt Handling
The I/O APIC handles interrupts very differently than the 8259. Briefly, these
differences are:
SMI/NMI/INIT/ExtINT Delivery Modes
These delivery modes are not supported by the Intel
reasons:
NMI/INIT: This signal has issues with delivery under power management. It cannot be
delivered while the processor is in the Stop Grant state. In addition, this is a break
event for power management. Breaking on the APIC bus message is more difficult than
breaking on the pin.
SMI: On the 82093, the I/O APIC could deliver the SMI through the pin SMIOUT# or as
an APIC bus message. When the message was masked by the OS, then the SMIOUT#
will be used. In other words, there is no way to block the delivery of the SMI#, except
through BIOS. Adding this interrupt to the I/O APIC only increases validation time.
•
•
•
•
Method of Interrupt Transmission. Interrupts are handled without the need for
the processor to run an interrupt acknowledge cycle. The Intel® 6300ESB ICH only
supports FSB delivery of interrupts.
Interrupt Priority. The priority of interrupts in the I/O APIC is independent of the
interrupt number. For example, interrupt 10 may be given a higher priority than
interrupt 3.
More Interrupts. The I/O APIC in the Intel
interrupts.
Multiple Interrupt Controllers. The I/O APIC interrupt transmission protocol has
an arbitration phase, which allows for multiple I/O APICs in the system with their
own interrupt vectors. The Intel
APIC bus before transmitting its interrupt message.
®
6300ESB ICH: APIC0 and APIC1 (device 29, function
®
6300ESB ICH I/O APIC must arbitrate for the
®
6300ESB ICH does not implement Hub
®
6300ESB ICH supports a total of 24
®
6300ESB ICH for the following
Intel
®
6300ESB I/O Controller Hub
®
6300ESB ICH.
121
DS