NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 490

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

11.1.6
Table 384. Offset 0Bh: Base Class Code
11.1.7
Table 385. Offset 0Dh: Master Latency Timer
11.1.8
Table 386. Offset 10 - 13h: Memory Base Address
Intel
DS
490
31:1
Bits
Bits
Bits
Default Value:
Default Value:
Default Value:
7:0
7:0
9:4
2:1
0
3
0
®
6300ESB I/O Controller Hub
Device:
Device:
Device:
Resource Type Indicator
Offset:
Offset:
Offset:
Master Latency Timer
Base Class Code
Base Address
Prefetchable
Offset 0Bh: Base Class Code
Offset 0Dh: Master Latency Timer
Offset 10 - 13h: Memory Base Address
Reserved
29
0Bh
0Ch
Name
29
0Dh
00h
Name
29
10 - 13h
00000000h
Name
(RTE)
Type
A value of 0Ch indicates that this is a Serial Bus controller.
Since the USB EHCI controller is internally implemented with
arbitration through the Hub Interface (and not PCI), it does
not need a master latency timer. These bits will be fixed to 0.
Bits [31:10] correspond to memory address signals [31:10],
respectively. This gives 1 Kbyte of locatable memory space
aligned to 1 Kbyte boundaries.
Reserved.
This bit is hardwired to 0, indicating that this range should
not be prefetched.
This field is hardwired to 00b indicating that this range may
be mapped anywhere within 32-bit address space.
This field is hardwired to 00b indicating that this range may
be mapped anywhere within 32-bit address space.
Description
Description
Description
Attribute:
Attribute:
Attribute:
Function:
Function:
Function:
Size:
Size:
Size:
7
Read-Only
8-bit
7
Read-Only
8-bit
7
Read/Write
32-bit
Order Number: 300641-004US
Intel
®
6300ESB ICH—11
November 2007
Access
Access
Access
RW
RO
RO
RO
RO
RO