NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 193

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

5—Intel
5.16.2
5.16.3
Table 85.
5.16.4
November 2007
Order Number: 300641-004US
Warning:Software must be careful when programming the comparator registers. When
®
6300ESB ICH
Timer Accuracy
The main counter will be clocked by the 14.31818 MHz clock, synchronized into the
66.666 MHz domain. This will result in a non-uniform duty cycle on the synchronized
clock, but does have the correct average period. The main counter will be as accurate
as the 14.3818 MHz clock.
Interrupt Mapping
Mapping Option #1: Legacy Option
In this case, the Legacy Rout bit (LEG_RT_CNF) will be set. This will force the mapping
found in
LEG_RT_CNF details.
Legacy Routing
Mapping Option #2: Standard Option
In this case, the Legacy Rout bit (LEG_RT_CNF) will be zero. Each timer has its own
routing control. The supported interrupt values are IRQ 20, 21, 22, and 23. See
Section 15.1.3, “Offset 010-017h: General Config Register”
Periodic vs. Non-Periodic Modes
Non-Periodic Mode
When a timer is set up for non-periodic mode, it will generate a value in the main
counter which matches the value in the timer’s comparator register. When the timer is
set up for 32-bit mode, it will generate another interrupt when the main counter wraps
around and matches this same value again. Timer 0 is configurable to 32 (default) or
64-bit mode, whereas Timers 1 and 2 only support 32-bit mode.
During run-time, the value in the timer’s comparator value register will not be changed
by the hardware. Software may change the value.
the value written to the register is not sufficiently far in the future, the counter
1. The timers are accurate over any 1 ms period to within 0.005% of the time
2. Within any 100 ms period, the timer will report a time that is up to two ticks too
3. The timer is monotonic. It will not return the same value on two consecutive reads
Time
0
1
2
r
specified in the timer resolution fields.
early or too late. Each tick is less than or equal to 100 ns, so this represents an
error of less than 0.2%.
(unless the counter has rolled over and reached the same value).
Table
Routing Field
As per IRQ
Mapping
8259
IRQ0
IRQ8
85. See
Section 15.1.3, “Offset 010-017h: General Config Register”
Routing Field
As per IRQ
Mapping
APIC
IRQ2
IRQ8
In this case, the 8254 timer will not cause any
interrupts.
In this case, the RTC will not cause any interrupts.
Comment
Intel
for LEG_RT_CNF details.
®
6300ESB I/O Controller Hub
for
193
DS