NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 310

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

7.1.32
Table 178. Offset 92h: ERR_STS—Error Status Register (HUB-PCI—D30:F0)
7.1.33
Table 179. Offset F8h - FBh: MANID— Manufacturer’s ID
Intel
DS
310
31:1
15:8
Bits
Bits
Default Value:
Default Value:
7:3
1:0
7:0
2
6
®
6300ESB I/O Controller Hub
Lockable:
Lockable:
Note: This register records the cause of system errors in Device 30. The actual assertion of
Device:
Device:
SERR# Due to Received
Offset:
Offset:
Manufacturer
Target Abort
(SERR_RTA)
Process/Dot
Offset 92h: ERR_STS—Error Status Register
(HUB-PCI—D30:F0)
SERR# is enabled through the PCI Command register.
Offset F8h - FBh: MANID— Manufacturer’s ID
Reserved
Reserved
Reserved
30
92h
00h
No
Name
30
F8h-FBh
0000 0F66h
No
Name
Reserved.
0 = This bit is cleared by writing a 1.
1 = Intel
Reserved. Bit 1 was the SERR# Enabled for Delayed
Transaction Timeout, see
BRIDGE_CNT—Bridge Control Register
Reserved.
0Fh = Intel
66h = Process 859.6
6300ESB ICH receives a target abort. When SERR_EN,
the Intel
when SERR_RTA is set.
®
6300ESB ICH sets this bit when the Intel
®
6300ESB ICH will also generate an SERR#
Power Well:
Power Well:
Description
Description
Section 7.1.24, “Offset 3E - 3Fh:
Attribute:
Attribute:
Function:
Function:
Size:
Size:
0
Read/Write
8-bit
Core
0
Read-Only
32-bit
Core
(HUB-PCI—D30:F0)”.
Order Number: 300641-004US
®
Intel
®
6300ESB ICH—7
November 2007
Access
Access
R/W
RO
RO