NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 370

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

Table 251. DAT—Data Register
8.5.4
Table 252. Offset FEC0_0020h: IRQPA—IRQ Pin Assertion Register
8.5.5
Intel
DS
370
31:5
Bits
Bits
Default Value:
Default Value:
7:0
4:0
®
6300ESB I/O Controller Hub
Note: The IRQ Pin Assertion Register is present to provide a mechanism to scale the number
Note: Writes to this register are only allowed by the processor and by masters on the Intel
Note: This is similar to what already occurs when the APIC sees the EIO message on the
Device:
Device:
Offset:
Offset:
IRQ Number
APIC Data
Offset FEC0_0020h: IRQPA—IRQ Pin Assertion
Register
of interrupt inputs into the I/O APIC without increasing the number of dedicated input
pins. When a device that supports this interrupt assertion protocol requires interrupt
service, that device will issue a write to this register. Bits 4:0 written to this register
contain the IRQ number for this interrupt. The only valid values are 0-23. Bits 31:5 are
ignored. To provide for future expansion, peripherals should always write a value of 0
for Bits 31:5.
See
this field.
6300ESB ICH’s PCI bus. Writes by devices on PCI buses above the Intel
are not supported.
Offset FEC0 - EOIR: EOI Register
The EOI register is present to provide a mechanism to maintain the level triggered
semantics for level-triggered interrupts issued on the parallel bus.
When a write is issued to this register, the I/O APIC will check the lower eight bits
written to this register, and compare it with the vector field for each entry in the I/O
Redirection Table. When a match is found, the Remote_IRR bit for that I/O Redirection
Entry will be cleared.
serial bus. Note that if multiple I/O Redirection entries, for any reason, assign the same
Reserved
31
FEC0_0010h
00000000h
Name
31
FEC0_0020h
N/A
Name
Section 5.7.4, “Interrupt Mapping”
This is a 32-bit register for the data to be read or written to
the APIC indirect register pointed to by the Index register.
Reserved. To provide for future expansion, the processor
should always write a value of 0 to Bits 31:5.
Bits 4:0 written to this register contain the IRQ number for
this interrupt. The only valid values are 0-23.
Description
Description
for more details on how PCI devices will use
Attribute:
Attribute:
Function:
Function:
Size:
Size:
0
Read/Write
32-bit
0
Write-Only
32-bit
Order Number: 300641-004US
Intel
®
®
6300ESB ICH—8
6300ESB ICH
November 2007
Access
Access
R/W
WO
®