NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 123
NHE6300ESB S L7XJ
Manufacturer Part Number
NHE6300ESB S L7XJ
Description
Manufacturer
Intel
Datasheet
1.NHE6300ESB_S_L7XJ.pdf
(848 pages)
Specifications of NHE6300ESB S L7XJ
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5—Intel
5.7.4
Table 44.
November 2007
Order Number: 300641-004US
®
6300ESB ICH
Interrupt Mapping
Only level-triggered interrupts can be shared. PCI interrupts (PIRQs and PXIRQs) are
inherently shared on the board; these should, therefore, be programmed as level-
triggered.
The following tables show the mapping of the various interrupts in Non-APIC and APIC
modes.
Interrupt Mapping in Non-APIC
There are two APICS within the Intel
each. APIC0 and APIC1 (Device 29 Function 5). APIC0 supports PCI messages interrupt
from external device. Each interrupt has its own unique vector assigned by software.
The interrupt vectors are mapped as follows.
NOTES:
1. If an interrupt is used for Boot interrupt, PCI IRQ[A:H], SCI, or TCO, it should not be used for
2. In non-APIC mode, the PCI interrupts are mapped to IRQ3, 4, 5, 6, 7, 9, 10, 11, 12, 14, or
3. IRQ 14 and 15 can only be driven directly from the pins when in Legacy IDE mode.
4. If IRQ11 is used for MMT #2, software should ensure IRQ 11 is not shared with any other
5. SW: Boot interrupt may optionally be routed to PIRQG# output for programmable PIRQx#
IRQ #
ISA-style interrupts (via SERIRQ or IRQ14/15 pins). IRQ9 will be default to boot interrupt.
15.
devices to ensure the proper operation of MMT #2. The Intel
prevent sharing of IRQ 11.
mapping.
10
11
12
13
14
15
0
1
2
3
4
5
6
7
8
9
Via SERIRQ
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
Direct from
Yes
Yes
Pin
No
No
No
No
No
No
No
No
No
No
No
No
No
No
3
3
Non-APIC Mode
®
6300ESB ICH supporting 24 APIC interrupts
8254 Counter 0, MMT#0
8259 #2 cascade only
Option for PIRQx
Option for PIRQx
Option for PIRQx
Option for PIRQx
Option for PIRQx
RTC, MMT#1
Option for PIRQx, SCI, TCO, boot interrupt
Option for PIRQx, SCI, TCO
Option for PIRQx, SCI, TCO, MMT #2
Option for PIRQx
FERR# Logic
PIRQx, Storage (IDE/SATA) Primary (legacy mode)
PIRQx, Storage (IDE/SATA) Secondary (legacy
mode)
Internal Modules
®
6300ESB ICH does not
Intel
®
6300ESB I/O Controller Hub
123
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