NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 424

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

8.9.11
Table 311. Offset TCOBASE + OEh: TCO_WDSTATUS—TCO2 Control Register
8.9.12
Table 312. Offset TCOBASE + 10h: SW_IRQ_GEN—Software IRQ Generation
Intel
DS
424
Bits
Bits
Default Value:
Default Value:
7:0
7:2
1
0
®
6300ESB I/O Controller Hub
Lockable:
Lockable:
Device:
Device:
Offset:
Offset:
WDSTATUS: Watchdog
IRQ12_CAUSE
IRQ1_CAUSE
Offset TCOBASE + OEh: TCO_WDSTATUS—TCO2
Control Register
Offset TCOBASE + 10h: SW_IRQ_GEN—Software
IRQ Generation Register
Register
Reserved
Status
31
TCOBASE + 0Eh
00h
No
Name
31
TCOBASE + 10h
11h
No
Name
The value written to this register can be passed via SMBus to
an External LAN controller. It may be used by the BIOS or
system management software to indicate more details on the
boot progress. This register will be reset to the default of 00h
based on RSMRST# (but not PCI reset).
Reserved.
The state of this bit is logically ANDed with the IRQ12 signal
as received by the Intel
bit must be a ‘1’ (default) when the Intel
expected to receive IRQ12 assertions from a SERIRQ device.
The state of this bit is logically ANDed with the IRQ1 signal as
received by the Intel
must be a ‘1’ (default) when the Intel
expected to receive IRQ1 assertions from a SERIRQ device.
®
6300ESB ICH’s SERIRQ logic. This bit
Power Well:
Power Well:
®
Description
Description
Attribute:
Attribute:
6300ESB ICH’s SERIRQ logic. This
Function:
Function:
Size:
Size:
0
Read/Write
8-bit
Resume
0
Read/Write
8-bit
Core
®
6300ESB ICH is
®
6300ESB ICH is
Order Number: 300641-004US
Intel
®
6300ESB ICH—8
November 2007
Access
Access
R/W
R/W
R/W