NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 537

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

12—Intel
12.2.2
November 2007
Order Number: 300641-004US
Bits
Default Value:
7
6
5
Table 441. Offset 02h: HST_CNT—Host Control Register (Sheet 1 of 3)
Note: A read to this register will clear the byte pointer of the 32-byte buffer.
Device:
®
Offset:
6300ESB ICH
LAST_BYTE
Offset 02h: HST_CNT—Host Control Register
PEC_EN
31
02h
00h
Name
START
0 = SMBus host controller does not perform the transaction
1 = Causes the host controller to perform the SMBus
0 = This bit will always return ’0’ on reads. The HOST_BUSY
1 = Writing a ’1’ to this bit initiates the command described in
This bit is used for Block Read commands.
1 = Software sets this bit to indicate that the next byte will be
NOTE: Once the SECOND_TO_STS bit in TCO2_STS register
with the PEC phase appended.
transaction with the Packet Error Checking phase
appended. For writes, the value of the PEC byte is
transferred from the PEC Register. For reads, the PEC
byte is loaded into the PEC Register. This bit must be
written prior to the write in which the START bit is set.
bit in the Host Status register (offset 00h) may be used
to identify when the Intel
command.
the SMB_CMD field. All registers should be setup prior to
writing a ‘1’ to this bit position.
the last byte to be received for the block. This causes the
Intel
after receiving the last byte.
(D31:F0, TCOBASE+6h, bit 1) is set, the LAST_BYTE
bit also gets set. While the SECOND_TO_STS bit is
set, the LAST_BYTE bit cannot be cleared. This
prevents the Intel
of the SMBus commands (Block Read/Write, I
Block I
®
6300ESB ICH to send a NACK (instead of an ACK)
2
C Write).
Description
®
Attribute:
Function:
6300ESB ICH from running some
®
Size:
6300ESB ICH has finished the
3
Read/Write
8-bit
Intel
®
2
C Read,
6300ESB I/O Controller Hub
Access
R/W
WO
WO
537
DS