NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 115

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

5—Intel
5.6.1.2
Table 43.
5.6.1.3
5.6.2
November 2007
Order Number: 300641-004US
®
6300ESB ICH
Acknowledging Interrupts
The processor generates an interrupt acknowledge cycle which is translated by the host
bridge into a PCI Interrupt Acknowledge Cycle to the Intel
translates this command into two internal INTA# pulses expected by the 8259 cores.
The PIC uses the first internal INTA# pulse to freeze the state of the interrupts for
priority resolution. On the second INTA# pulse, the master or slave will send the
interrupt vector to the processor with the acknowledged interrupt code. This code is
based upon bits [7:3] of the corresponding ICW2 register, combined with three bits
representing the interrupt within that controller.
Content of Interrupt Vector Byte
Hardware/Software Interrupt Sequence
Initialization Command Words (ICWx)
Before operation may begin, each 8259 must be initialized. In the Intel
this is a four byte sequence. The four initialization command words are referred to by
their acronyms: ICW1, ICW2, ICW3, and ICW4.
1. One or more of the Interrupt Request lines (IRQ) are raised high in edge mode, or
2. The PIC sends INTR active to the processor when an asserted interrupt is not
3. The processor acknowledges the INTR and responds with an interrupt acknowledge
4. Upon observing its own interrupt acknowledge cycle on PCI, the Intel
5. Upon receiving the first internally generated INTA# pulse, the highest priority ISR
6. Upon receiving the second internally generated INTA# pulse, the PIC returns the
7. This completes the interrupt cycle. In AEOI mode the ISR bit is reset at the end of
seen high in level mode, setting the corresponding IRR bit.
masked.
cycle. The cycle is translated into a PCI interrupt acknowledge cycle by the host
bridge. This command is broadcast over PCI by the Intel
ICH converts it into the two cycles that the internal 8259 pair may respond to. Each
cycle appears as an interrupt acknowledge pulse on the internal INTA# pin of the
cascaded interrupt controllers.
bit is set and the corresponding IRR bit is reset. On the trailing edge of the first
pulse, a slave identification code is broadcast by the master to the slave on a
private, internal three bit wide bus. The slave controller uses these bits to
determine when it must respond with an interrupt vector during the second INTA#
pulse.
interrupt vector. When no interrupt request is present because the request was too
short in duration, the PIC will return vector 7 from the master controller.
the second INTA# pulse. Otherwise, the ISR bit remains set until an appropriate
EOI command is issued at the end of the interrupt subroutine.
Master, Slave Interrupt
IRQ7,15
IRQ6,14
IRQ5,13
IRQ4,12
IRQ3,11
IRQ2,10
IRQ1,9
IRQ0,8
Bits [7:3]
ICW2[7:3]
®
Intel
6300ESB ICH. The PIC
®
6300ESB ICH.
®
6300ESB I/O Controller Hub
Bits [2:0]
®
111
110
101
100
011
010
001
000
6300ESB ICH,
®
6300ESB
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