NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 397

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

8—Intel
8.8.3.3
Table 286. PM1_CNT—Power Management 1 Control
November 2007
Order Number: 300641-004US
31:1
12:1
Bits
Default Value:
9:3
13
I/O Address:
4
0
2
1
0
Lockable:
®
Note: Usage: ACPI or Legacy.
Device:
6300ESB ICH
SLP_EN: Sleep Enable
SLP_TYP: Sleep Type
SCI_EN: SCI Enable
GBL_RLS: Global
PM1_CNT—Power Management 1 Control
Reserved
Reserved
Reserved
Release
31
PMBASE + 04h
(ACPI PM1a_CNT_BLK)
00000000h
No
Name
Reserved.
Setting this bit causes the system to sequence into the Sleep
state defined by the SLP_TYP field.
This 3-bit field defines the type of Sleep the system should
enter when the SLP_EN bit is set to 1.
000 = ON: Typically maps to S0 state.
001 = Asserts STPCLK#. Puts CPU in Stop-Grant state.
Optional to assert CPUSLP# to put CPU in sleep state:
Typically maps to S1 state.
010 = Reserved
011 = Reserved
100 = Reserved
101 = Suspend-To-RAM. Assert SLP_S1# and SLP_S3#:
Typically maps to S3 state.
110 = Suspend-To-Disk. Assert SLP_S1#, SLP_S3#, and
SLP_S4#: Typically maps to S4 state.
111 = Soft Off. Assert SLP_S1#, SLP_S3#, SLP_S4#, and
SLP_S5#: Typically maps to S5 state.
NOTE: These bits are only reset by RTCRST#.
Reserved.
0 = This bit always reads as 0.
1 = ACPI software writes a 1 to this bit to raise an event to
Reserved.
Selects the SCI interrupt or the SMI# interrupt for various
events including the bits in the PM1_STS register (bit 10, 8,
0), and bits in GPE0_STS.
0 = These events will generate an SMI#.
1 = These events will generate an SCI.
the BIOS. BIOS software has a corresponding enable and
status bits to control its ability to receive ACPI events.
Power Well:
Description
Attribute:
Function:
Size:
0
Read/Write
32-bit
Bits 0-7: Core,
Bits 8-12: RTC
Bits 13-15: Resume
Intel
®
6300ESB I/O Controller Hub
Access
R/W
R/W
WO
WO
397
DS