NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 539

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

12—Intel
12.2.3
12.2.4
November 2007
Order Number: 300641-004US
Bits
Bits
Bits
Default Value:
Default Value:
Default Value:
7:0
1
0
Table 441. Offset 02h: HST_CNT—Host Control Register (Sheet 3 of 3)
Table 442. Offset 03h: HST_CMD—Host Command Register
Table 443. Offset 04h: XMIT_SLVA—Transmit Slave Address Register
Note: This register is transmitted by the host controller in the slave address field of the
Device:
Device:
Device:
®
Offset:
Offset:
Offset:
6300ESB ICH
Offset 03h: HST_CMD—Host Command Register
Offset 04h: XMIT_SLVA—Transmit Slave Address
Register
SMBus protocol.
ADDRESS
INTREN
31
02h
00h
Name
31
03h
00h
Name
31
04h
00h
Name
KILL
RW
0 = Normal SMBus Host Controller functionality.
1 = When set, kills the current host transaction taking place,
0 = Disable.
1 = Enable the generation of an interrupt or SMI# upon the
This 8-bit field is transmitted by the host controller in the
command field of the SMBus protocol during the execution of
any command.
7-bit address of the targeted slave.
Direction of the host transfer.
0 = Write
1 = Read
sets the FAILED status bit, and asserts the interrupt (or
SMI#). This bit, once set, must be cleared by software to
allow the SMBus Host Controller to function normally.
completion of the command.
Description
Description
Description
Attribute:
Attribute:
Attribute:
Function:
Function:
Function:
Size:
Size:
Size:
3
Read/Write
8-bit
3
Read/Write
8-bit
3
Read/Write
8-bit
Intel
®
6300ESB I/O Controller Hub
Access
Access
Access
R/W
R/W
R/W
R/W
R/W
539
DS