NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 763
NHE6300ESB S L7XJ
Manufacturer Part Number
NHE6300ESB S L7XJ
Description
Manufacturer
Intel
Datasheet
1.NHE6300ESB_S_L7XJ.pdf
(848 pages)
Specifications of NHE6300ESB S L7XJ
Lead Free Status / RoHS Status
Compliant
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20—Intel
20.1.38 Offset Index 54h - 57h: SER0—SATA SError
20.1.39 Offset Index 64h - 67h: SER1—SATA SError
20.1.40 Offset E0h - E3h: BFCS—BIST FIS Control/Status
November 2007
Order Number: 300641-004US
31:0
31:0
31:1
Bits
Bits
Bits
Default Value:
Default Value:
Default Value:
2
Table 697. Offset Index 54h - 57h: SER0—SATA SError Register Port 0 (SATA–
Table 698. Offset Index 64h - 67h: SER1—SATA SError Register Port 1 (SATA–
Table 699. Offset E0h - E3h: BFCS—BIST FIS Control/Status Register (SATA–
Device:
Device:
Device:
®
Offset:
Offset:
Offset:
6300ESB ICH
Register Port 0 (SATA–D31:F2)
D31:F2)
Register Port 1 (SATA–D31:F2)
D31:F2)
Register (SATA–D31:F2)
D31:F2)
Reserved
(Sheet 1 of 3)
31
Index 54h–57h
XXXXXXXXh
Name
31
Index 64h–67h
XXXXXXXXh
Name
31
E0h–E3h
00000000h
Name
SER0
SER1
This register is implemented in accordance with the SERROR
register description in Section 10.1.2 of the SATA 1.0
Specification.
This register is implemented in accordance with the SERROR
register description in Section 10.1.2 of the SATA 1.0
Specification.
Reserved.
Description
Description
Description
Attribute:
Attribute:
Attribute:
Function:
Function:
Function:
Size:
Size:
Size:
2
Read/Write
32-bit
2
Read/Write
32-bit
2
Read/Write, Read/Write Clear
32-bit
Intel
®
6300ESB I/O Controller Hub
Access
Access
Access
R/W
R/W
763
DS
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