NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 348

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

8.2.1
Table 220. DMABASE_CA—DMA Base and Current Address Registers
Intel
DS
348
15:0
Bits
Default Value:
I/O Address:
®
6300ESB I/O Controller Hub
Lockable:
Device:
Base and Current
DMABASE_CA—DMA Base and Current Address
Registers
Address
31
Ch. #0 = 00h; Ch. #1 =
02h, Ch. #2 = 04h; Ch.
#3 = 06h, Ch. #5 = C4h
Ch. #6 = C8h, Ch. #7 =
CCh
Undefined
No
Name
This register determines the address for the transfers to be
performed. The address specified points to two separate
registers. On writes, the value is stored in the Base Address
register and copied to the Current Address register. On reads,
the value is returned from the Current Address register.
The address increments/decrements in the Current Address
register after each transfer, depending on the mode of the
transfer. When the channel is in auto-initialize mode, the
Current Address register will be reloaded from the Base
Address register after a terminal count is generated.
For transfers to/from a 16-bit slave (channel’s 5-7), the
address is shifted left one bit location. Bit 15 will be shifted
into Bit 16.
The register is accessed in 8 bit quantities. The byte is
pointed to by the current byte pointer flip/flop. Before
accessing an address register, the byte pointer flip/flop should
be cleared to ensure that the low byte is accessed first
Power Well:
Description
Attribute:
Function:
Size:
0
Read-Only
16-bit, accessed in two 8-bit quantities
Core
Order Number: 300641-004US
Intel
®
6300ESB ICH—8
November 2007
Access
R/W