NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 607

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

15—Intel
15.1.3
November 2007
Order Number: 300641-004US
63:2
1
0
Bits
Default Value:
Table 530. Offset 010-017h: General Config Register
®
Offset:
ENABLE_CNF: Overall
6300ESB ICH
LEG_RT_CNF
Offset 010-017h: General Config Register
Reserved
Enable
010-017h
0000 0000 0000 0000h
Name
Reserved. These bits will return ’0’ when read.
Legacy Rout: When the ENABLE_CNF bit and the
LEG_RT_CNF bit are both set, the interrupts will be routed as
follows:
This bit must be set to enable any of the timers to generate
interrupts. When this bit is ‘0’, the main counter will halt (will
not increment) and no interrupts will be caused by any of
these timers. For level-triggered interrupts, if an interrupt is
pending when the ENABLE_CNF bit is changed from ’1’ to ‘0’,
the interrupt status indications in the various Txx_INT_STS
bits will not be cleared. Software must write to the
Txx_INT_STS bits to clear the interrupts.
NOTE: This bit will default to ‘0’. BIOS may set it to ’1’ or ‘0’.
• Timer 0 will be routed to IRQ0 in 8259 or IRQ2 in the I/O
• Timer 1 will be routed to IRQ8 in 8259 or IRQ8 in the I/O
• Timer 2-n will be routed as per the routing in the timer n
• When the Legacy Rout bit is set, the individual routing
• When the Legacy Rout bit is not set, the individual routing
• This bit will default to ‘0’. BIOS may set it to ’1’ to enable
APIC.
APIC.
config registers.
bits for Timers 0 and 1 (APIC) will have no impact.
bits for each of the timers are used.
the legacy routing or ’0’ to disable the legacy routing.
Description
Attribute:
Size:
Read/Write
64-bit
Intel
®
6300ESB I/O Controller Hub
Access
R/W
R/W
607
DS