NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 433

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

8—Intel
Table 321. Offset GPIOBASE + 38h: GP_LVL2—GPIO Level for Input or Output 2
November 2007
Order Number: 300641-004US
Implementation Note: Bits 26:31 may be in CORE Well.
23:1
11:0
Bits
Default Value:
2
Lockable:
®
Device:
Offset:
6300ESB ICH
GP_LVL2[43:32]
Register
Reserved
31
GPIOBASE +38h
00000FFFh
No
Name
Reserved. Read-only 0.
When GPIO[n] is programmed to be an output (through the
corresponding bit in the GP_IO_SEL2 register), the
corresponding GP_LVL2[n] bit may be updated by software to
drive a high or low value on the output pin. 1 = high, 0 = low.
When GPIO[n] is programmed as an input, then the
corresponding GP_LVL2 bit reflects the state of the input
signal (1 = high, 0 = low). Writes will have no effect.
Since these bits correspond to GPIO that are in the core well,
these bits will be reset by PXPCIRST#.
Power Well:
Description
Attribute:
Function:
Size:
0
Read/Write
32-bit
Core for 23:0, RTC for 31:24
Intel
®
6300ESB I/O Controller Hub
Access
RO
433
DS