NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 344

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

Table 216. Offset F2h: FUNC_DIS—Function Disable Register (LPC I/F—D31:F0)
Intel
DS
344
NOTE: Software must always disable all functionality within the function before disabling the configuration
Bits
Default Value:
3
2
1
0
®
6300ESB I/O Controller Hub
Lockable:
space.
Device:
Offset:
D31_F3_Disable
D31_F2_Disable
D31_F1_Disable
SMB_FOR_BIOS
(Sheet 2 of 2)
31
F2h
0080h
No
Name
Software sets this bit to disable the SMBus Host Controller
function. BIOS must not enable I/O or memory address space
decode, interrupt generation, or any other functionality of
functions that are to be disabled
0 = SMBus controller is enabled
1 = SMBus controller is disabled
Software sets this bit to disable the SATA Controller function.
BIOS must not enable I/O or memory address space decode,
interrupt generation, or any other functionality of functions
that are to be disabled
0 = SATA controller is enabled
1 = SATA controller is disabled
Software sets this bit to disable the IDE controller function.
BIOS must not enable I/O or memory address space decode,
interrupt generation, or any other functionality of functions
that are to be disabled
0 = IDE controller is enabled
1 = IDE controller is disabled
This bit is used in conjunction with bit 3 in this register.
0 = No effect.
1 = Allows the SMBus I/O space to be accessible by software
when bit 3 in this register is set. The PCI configuration
space is hidden in this case. Note that when bit 3 is set
alone, the decode of both SMBus PCI configuration and I/
O space will be disabled.
.
.
Power Well:
Description
Attribute:
Function:
Size:
.
0
Read/Write
16-bit
Core
Order Number: 300641-004US
Intel
®
6300ESB ICH—8
November 2007
Access
R/W
R/W
R/W
R/W