NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 681

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

18—Intel
18.6.1.32Offset E4: PCR - PCI Compensation Register
November 2007
Order Number: 300641-004US
15:1
08:0
Bits
09
0
Table 615. Offset E4: PCR - PCI Compensation Register
SBR Enable
®
Device
Offset
Reserved
Reserved
6300ESB ICH
(SBRE)
Name
28
E4
Reserved.
This field specifies the maximum size write a master should
request in a single b
0 = PCI-X secondary bus reset (PCIXSBRST#) disabled and
1 = PCI-X secondary bus reset (PCIXSBRST#) enabled and
NOTE: Processor always writes a ’1’ into this bit and enables
Reserved.
SBR bit has no effect. See
BCTRL—Bridge
SBR is set.
the secondary bus reset for the PCI-X bus.
Control”, bit 6, for SBR details.
Description
Section 18.6.1.21, “Offset 3E:
Attribute:
Function
Size:
0
Read/Write
16-bit
Intel
®
Reset
Value
6300ESB I/O Controller Hub
0
0
0
Access
R/W
R/W
R/W
681
DS