NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 558

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

13.1.13 Offset 1C - 1Fh: MBBAR—Bus Master Base Address
Intel
DS
558
31:8
Bits
Bits
Default Value:
Default Value:
8:3
2:1
7:3
2:1
0
0
®
Table 471. Offset 18 - 1Bh: MMBAR—Mixer Base Address Register (Audio—
Table 472. Offset 1C - 1Fh: MBBAR—Bus Master Base Address Register
6300ESB I/O Controller Hub
Lockable:
Lockable:
Note: This BAR creates 256 bytes of memory space to signify the base address of the bus
Device:
Device:
Resource Type Indicator
Resource Type Indicator
Offset:
Offset:
Base Address
D31:F5) (Sheet 2 of 2)
Register (Audio—D31:F5)
master memory space. The lower 64 bytes of the space pointed to by this register point
to the same registers as the NABMBAR.
(Audio—D31:F5)
Reserved
Reserved
31
18-1Bh
00000000h
No
Name
31
1C-1Fh
00000000h
No
Name
(RTE)
(RTE)
Type
Type
Reserved. Read as ‘0’s.
Indicates the base address exists in 32-bit address space
This bit is set to ’0’, indicating a request for memory space.
I/O offset to use for decoding the PCM In, PCM Out, and
Microphone 1 DMA engines.
Reserved. Read as ‘0’s.
Indicates the base address exists in 32-bit address space.
This bit is set to ’0’, indicating a request for memory space.
Power Well:
Power Well:
Description
Description
Attribute:
Attribute:
Function:
Function:
Size:
Size:
5
Read/Write
32-bit
Core
5
Read/Write
32-bit
Core
Order Number: 300641-004US
Intel
®
6300ESB ICH—13
November 2007
Access
Access
R/W
RO
RO
RO
RO
RO
RO