NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 446

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

9.1.17
9.1.18
Intel
DS
446
15:0
Bits
Bits
Default Value:
Default Value:
7:0
®
Table 339. Offset 2Eh - 2Fh: IDE_SID—Subsystem ID (IDE—D31:F1)
Table 340. Offset 3Ch: INTR_LN—Interrupt Line Register (IDE—D31:F1)
6300ESB I/O Controller Hub
Lockable:
Device:
Device:
Offset:
Offset:
Subsystem ID (SID)
Interrupt Line
Offset 2Eh - 2Fh: IDE_SID—Subsystem ID (IDE—
D31:F1)
Offset 3Ch: INTR_LN—Interrupt Line Register
(IDE—D31:F1)
31
2Eh-2Fh
0000h
No
Name
31
3Ch
00h
Name
The SID register, in combination with the SVID register,
enables the operating system (OS) to distinguish subsystems
from each other. Software (BIOS) sets the value in this
register. After that, the value may be read, but subsequent
writes to this register have no effect. The value written to this
register will also be readable through the corresponding SID
registers for the USB UHCI #1, USB UHCI #2, and SMBus
functions.
NOTE: Write accesses to the SID register should only be
This data is not used by the Intel
communicate to software the interrupt line which the
interrupt pin is connected to.
done as 16-bit accesses. If two 8-bit write accesses
are done, then the value in the register will not be
correct.
Power Well:
Description
Description
Attribute:
Attribute:
Function:
Function:
Size:
Size:
®
6300ESB ICH. It is used to
1
Read/Write Once
16-bit
Core
1
Read/Write
8-bit
Order Number: 300641-004US
Intel
®
6300ESB ICH—9
R/Write-Once
November 2007
Access
Access
R/W